I think that if we *do* see quads any time , there will probably be only one model, with support for 8 or 16GB of memory. It would also have a different enclosure - maybe a thicker XServe form factor, or two powermacs welded together
Supporting 4 separate busses will require one freaking expensive controller though, maybe the processors will share.. or use some freaky technology alluded to in the demented ramblings of the members of this forum.
I think that if we *do* see quads any time , there will probably be only one model, with support for 8 or 16GB of memory. It would also have a different enclosure - maybe a thicker XServe form factor, or two powermacs welded together
Supporting 4 separate busses will require one freaking expensive controller though, maybe the processors will share.. or use some freaky technology alluded to in the demented ramblings of the members of this forum.
The dual core chips will be bigger, hotter, and more power hungry, and based on the cooling that they've had to put in the new G5s it'd seem like the current cooling system is being pushed to the limit..
You do have a point though, perhaps just a slightly larger G5 tower would do the trick. That would also solve the bus problem (assuming dual-core chips share a bus).
Would dual-core chips share cache? I'm not sure if that would be a good thing or a bad thing...
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Supporting 4 separate busses will require one freaking expensive controller though, maybe the processors will share.. or use some freaky technology alluded to in the demented ramblings of the members of this forum.
Originally posted by dfryer
I think that if we *do* see quads any time , there will probably be only one model, with support for 8 or 16GB of memory. It would also have a different enclosure - maybe a thicker XServe form factor, or two powermacs welded together
Supporting 4 separate busses will require one freaking expensive controller though, maybe the processors will share.. or use some freaky technology alluded to in the demented ramblings of the members of this forum.
Or just dual dual-core chips.
You do have a point though, perhaps just a slightly larger G5 tower would do the trick. That would also solve the bus problem (assuming dual-core chips share a bus).
Would dual-core chips share cache? I'm not sure if that would be a good thing or a bad thing...
Originally posted by dfryer
Would dual-core chips share cache? I'm not sure if that would be a good thing or a bad thing...
POWER5 cores share a single L2 cache but each has its own L1 data and L1 instruction cache. It's not a bad thing. Read more here.