Pardon me, lets revisit the DDR "hack"

in Current Mac Hardware edited January 2014
Pardon me, ladies and gentleworms... but I entered this here little board after the discussion about the XSERVE and why its DDR capabilities are a "hack." I will apologize in advance for such tomfoolery, but I am wondering what the real difference is between the "hacked" DDR and true DDR. What does either of them mean in terms of the upcoming PowerMac? Will we see TRUE DDR, and how much will it outperform the hacked DDR?

<img src="confused.gif" border="0">


  • Reply 1 of 7
    davegeedavegee Posts: 2,765member
    One word: 'search'

    Three words: 'not future hardware'
  • Reply 2 of 7
    rickagrickag Posts: 1,626member
    The cpu communicates @ DDR rates w/ the ram ONLY. The cpu communicates on the FSB still only at 133MHz.

    Remember that the ram can be accessed w/ DMA direct memory access, not using the FSB.

    in under the lock
  • Reply 3 of 7
    Two words: SMART ASS.

  • Reply 4 of 7
    jambojambo Posts: 3,036member
    Moving this over to Current Hardware...
  • Reply 5 of 7
    stoostoo Posts: 1,490member
    The XServe's use of DDR SDRAM is referred to as a "hack" because the processors' bus is slower than the RAM. The bus the G4 CPUs connect to the motherboard on has a clock rate of 133MHz and can transfer 64bits of data once per clock pulse ("single data rate"), giving a bandwidth 64*133*10^6 bits per second, or roughly one gigabyte per second. This is shared between both CPUs.

    The DDR SDRAM used in the XServe has a clock rate of 133MHz and can transfer 64bits of data twice ("double data rate") per clock pulse, giving it a (theoretical) bandwidth of roughly 2 gigabytes per second, more than the bandwidth available on the CPUs' bus.

    A few points:
    • More than the CPUs use the memory. The dual gigabit ethernet cards, hard drives and AGP transfers can access memory directly (DMA), largely independently of the CPU.

    • "True" DDR refers to the bandwidth of the CPUs' bus and memory matching more closely. This may be by the G4++, nay, next desktop PowerPC to find its way into the PowerMac, gaining a double data rate bus and/or a faster bus clock rate.

    • The quoted bandwidths are theoretical and hard to achieve in practice. The G4's MPX bus protocol is quite efficient, and it is possible that it can consume data faster than single data rate SDRAM can provide it.

    • As mentioned on the Ars forums, Altivec is bandwidth starved by the G4's bus, so "true" DDR could improve Altivec performance considerably. Have to wait and see on the performance front...

  • Reply 6 of 7
    macaddictmacaddict Posts: 1,055member
    [quote]The bus the G4 CPUs connect to the motherboard <hr></blockquote>

    Correct me if you're wrong, but you sure you don't mean northbridge?

    G4s connect to the motherboard via a daughtercard. Or ZIF socket. Or something.
  • Reply 7 of 7
    stoostoo Posts: 1,490member
    OK, OK, they connect to a Nortbridge chipset type thing.
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