System Bus: Fact and Fiction

Posted:
in Current Mac Hardware edited January 2014
In reference to complaints that the bus on the two high end PowerMacs still are way below PC's, here's Apples response:



The two new systems come with a 167MHz system bus, though that's still well behind a 533MHz front-side setup for the fastest Pentium 4 systems.



But Greg Joswiak (of Apple) defended what apparently is a small increase in the system bus.



"Our architecture is tough to compare to a PC bus, because we don't run everything off the same bus the way a PC does," he said. "A PC may have a 533MHz bus, but it's putting everything through that bus--whereas, we put everything on its own dedicated bus."

Comments

  • Reply 1 of 2
    randycat99randycat99 Posts: 1,919member
    I suppose it depends on how well that FSB gets implemented, which I'm told works rather well on Apple's chips.



    The 533 bus on the P4 is actually a quad-data rate 133 Mhz bus. On average, maybe half the bandwidth is available in real use? At worse (depending on poor data flow and cache conflicts, not to mention trying to synchronize up to a CPU running at many times more clock rate), it may be chugging away as if it was a single 133 Mhz bus.



    Looking on the brightside, now that 333 is supported on the motherboard, we will be ready to rock once we do get a CPU that does support a DDR FSB. Progress moves in babysteps sometimes, and you just have to deal, IMO.



    The real problem is that Altivec. When running at full tilt, that thing is going to blow-out just about any FSB you throw at it, anyway, barring something absurd (something 128-bit wide, clocked at 1-2 Ghz, maybe?). Maybe if they were to implement some wacko secondary bus that gives Altivec a direct line to memory? Something sequential, but running at insane clock? ...But then RAM throughput would probably be the limiting factor? Problems, problems... At the least, the primary bus would stay vacant and functional for general CPU ops while the Altivec is grinding away.



    Is there any obstacle towards a CPU that has a primary system bus and a secondary, serial system bus? I guess the motherboard would be one. We just now get DDR on the motherboard, so who knows if it is open for any more big changes so early in life.



    Sorry to hijack the topic focus. Please do continue discussing the merits of Apple's system bus implementation vs. Intel's.



    [ 08-13-2002: Message edited by: Randycat99 ]</p>
  • Reply 2 of 2
    woozlewoozle Posts: 64member
    [quote]Originally posted by Randycat99:

    <strong>

    Is there any obstacle towards a CPU that has a primary system bus and a secondary, serial system bus? I guess the motherboard would be one. We just now get DDR on the motherboard, so who knows if it is open for any more big changes so early in life.



    [ 08-13-2002: Message edited by: Randycat99 ]</strong><hr></blockquote>



    Not really, this is exactly how the AMD Opteron works. It has a built in memory controller ( so in dual cpu systems each cpu could have its own dedicated memory bandwidth ), and uses Hypertransport to communicate with other devices ( CPU's, AGP, PCI ).

    It is a big boost for the CPU, improving latency and throughpupt, but will reduce the latency of devices on HT trying to access memory.



    It is the 'way of the future' for cpu's.



    For refernce, in memory benchmarks the Opteron running 333 DDR SDRAM ( dual channel I think ) can sustain 2.5 GB/s.



    The Pentium 4 can do about the same using RDRAM 1066 ( dual channel ).



    If the new G4's can scale, they should get about 25% more, or something like 1.2 GB/s.



    An Athon ( DDR 266 bus, 333 DDR SDRAM ) gets about 2GB/s ( and 1 GB/s with 133 SDRAM ). Although that is measured with Sisoft Sandra, and should be taken with a grain of salt ( its not nessecarily sustained - probably peak <a href="http://www.tomshardware.com/mainboard/02q2/020509/kt333-31.html"; target="_blank">http://www.tomshardware.com/mainboard/02q2/020509/kt333-31.html</a>;
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