Rambus XDR memory and Macs
Ok love'em or hate'em Rambus has some cool stuff coming and I think it may affect future Macs.
Rambus recently announced a memory controller that supports DDR, DDR2 and their new XDR. This is cool, "one memory controller to rule them all". This means the same memory controller could scale as follows.
eMac- Rambus Controller--> DDR
iMac-Rambus Controller--> DDR2
Powermac-Rambus Controller--> XDR
The Controller
Try the nifty Bandwidth Calculator
Here's a little tidbit on why Rambus XDR is special
Now keep in mind that GPU like the new Nvidia 6800 and ATI XT800 use GDDR3 which currently does about 50+ GBps throughput. Samsung is going to have a 1.4Ghz(2.8Ghz effective) part by the end of this year that supports 89GBps . The Rambus XDR may be competitive in this area.
Frankly the DDR2 roadmap isn't all that impressive. DDR2 667hz for 2005 and maybe 800 by 2006. That gives us PC6400 possibly.This in a Dual Channel config would give you 12.8GBps throughput. Using the calculator linked above it shows that
DDR- You'd need a 256bit memory interface with 32 componetns.
XDR- You'd need a 48bit memory interface with 3 components.
Looks like Apple might want to give themselves the most leverage with memory by keeping options open. XDR might just wipe DDR off the map. You can call Rambus a lot of things but with RDRAM they were indeed expensive but the benchmarks showed that bandwidth was indeed king. Latency wasn't hot then but look at DDR2 and it's poorer latency compared to DDR. Without a huge increase in bandwidth DDR2 is not a sure thing.
Rambus recently announced a memory controller that supports DDR, DDR2 and their new XDR. This is cool, "one memory controller to rule them all". This means the same memory controller could scale as follows.
eMac- Rambus Controller--> DDR
iMac-Rambus Controller--> DDR2
Powermac-Rambus Controller--> XDR
The Controller
Try the nifty Bandwidth Calculator
Here's a little tidbit on why Rambus XDR is special
Quote:
Key to XDR DRAM's draw is its high bandwidth per pin. Using a 400MHz clock, XDR can transmit eight data bits per clock (octal data rate) attaining a 3.2GHz/pin data rate. An 8-bit interface can transfer 3.2GBs/sec, and a 32-bit interface hits 12.8GB/sec. Tack two 32-bit "XDIMMS" together and you reach 25.6GB/sec at 3.2GHz signaling. Rambus expects to quickly move to 6.4GHz/pin signaling, so if you expand to a 128-bit interface at 6.4GHz/pin, you can reach 102.4GB/sec. This is far beyond speeds on DDR roadmaps. Rambus attains such speeds using three key technologies: Differential Rambus Signaling Levels (DRSL), FlexPhase technology (to compensate for timing errors), and octal data rate signaling mentioned previously. You can check out Rambus XDR info on their site for technical details.source: extremetech.com
Key to XDR DRAM's draw is its high bandwidth per pin. Using a 400MHz clock, XDR can transmit eight data bits per clock (octal data rate) attaining a 3.2GHz/pin data rate. An 8-bit interface can transfer 3.2GBs/sec, and a 32-bit interface hits 12.8GB/sec. Tack two 32-bit "XDIMMS" together and you reach 25.6GB/sec at 3.2GHz signaling. Rambus expects to quickly move to 6.4GHz/pin signaling, so if you expand to a 128-bit interface at 6.4GHz/pin, you can reach 102.4GB/sec. This is far beyond speeds on DDR roadmaps. Rambus attains such speeds using three key technologies: Differential Rambus Signaling Levels (DRSL), FlexPhase technology (to compensate for timing errors), and octal data rate signaling mentioned previously. You can check out Rambus XDR info on their site for technical details.source: extremetech.com
Now keep in mind that GPU like the new Nvidia 6800 and ATI XT800 use GDDR3 which currently does about 50+ GBps throughput. Samsung is going to have a 1.4Ghz(2.8Ghz effective) part by the end of this year that supports 89GBps . The Rambus XDR may be competitive in this area.
Frankly the DDR2 roadmap isn't all that impressive. DDR2 667hz for 2005 and maybe 800 by 2006. That gives us PC6400 possibly.This in a Dual Channel config would give you 12.8GBps throughput. Using the calculator linked above it shows that
DDR- You'd need a 256bit memory interface with 32 componetns.
XDR- You'd need a 48bit memory interface with 3 components.
Looks like Apple might want to give themselves the most leverage with memory by keeping options open. XDR might just wipe DDR off the map. You can call Rambus a lot of things but with RDRAM they were indeed expensive but the benchmarks showed that bandwidth was indeed king. Latency wasn't hot then but look at DDR2 and it's poorer latency compared to DDR. Without a huge increase in bandwidth DDR2 is not a sure thing.
Comments
Lets just hope.
Heavy hitters like
Matsushita
Toshiba and Samsung are intersted in using or making XDR modules.
I mean let's be honest here. The 1.25Ghz FSB for the Dual 2.5Ghz is nice but running it to a Dual Channel PC3200 bank of memory is still a large bottleneck. Both CPUs have to share the 6.4GBps bandwidth. Now we have Dual Core CPUs coming that will want even more. A Quad G5 would need at least 12,800GBps and even then it would be bottleneckng as we move towards 3Ggz. XDR will allow the bandwidth needs to be met without all the component connect costs. Rambus could be silly and price themselves out of consideration or they could be smart and keep grabbing marketshare.
Originally posted by Telomar
I believe the big win for XDR so far was the PS3.
Ah you beat me Telomar. I was going to add that but I thought I'd hold out. XDR requiring less pins but providing great bandwidth is a lynchpin of consoles and embedded devices that need to be as cost efficient as possible. I see desktops getting that way pretty damn soon when the memory controller has to support more than 2 CPU. A little simplicity will go a long way here.
I'm still waiting to find out how XDR handles 256 bit interfaces. I read that if it handles it as well as GDDR3 then it could become a boon for GPUs. Hard to believe we'll have GPUs that throughput almost 100GBps within a 18 months.
The approach they've taken is much like Rambus, but they have a memory controller on the DIMM, allowing any memory technology to be used, and installed along side others.
http://www.theinquirer.net/?article=15167
That was a good read. Here are all three articles. Looks like the next two years will provide more information on the future of memory.
Part One
Part Two
Part Three
Personally I'll wait to see some real world benchmarks first.
I guess as you say the benchmarks will have to tell the story. XDR may be relagated to embedded devices primarily.
I've always wondered if a 4 chip quad channel Rambus used as an off-chip cache would be useful. With 64 MB chips, that would make 256 MB of off-chip cache. With 3.2 GHz XDR chips, the bandwidth to the CPU would be 50 GB/s. Since only 1 chip per channel is used, latency should be very close, or perhaps better in some situations, than DDR. I bet a prospective 970 with such a cache would have 30% better FPU scores.
Worst case scenario we have a decent competition between FB-DIMM and XDR. Without XDR the JEDEC has no real incentive to keep licensing costs down.
There really isn't much downside to XDR. If you license the controller you can still use DDR or DDR2.
Originally posted by hmurchison
RDRAM did beat DDR in almost everthing beyond latency.
...and price.