different approach to MWSF2002
Everybody seems focused on the G5 for January 2002.
But no speculations of the G4 making another BIG clock rate step.
It might not mean too much but Motorola just silently released a new G4 version.
Also no specs on more Dual-Power-Macs or probably a Quad G4 hi-end-Mac.
I would guess more multi-CPU is not too likely but another significant step in Mhz could be possible.
Maybe even the smallest G4 Power Mac will be over 1 Ghz early next year.
If not I`d of course also be happy with the introduction of the G5
But no speculations of the G4 making another BIG clock rate step.
It might not mean too much but Motorola just silently released a new G4 version.
Also no specs on more Dual-Power-Macs or probably a Quad G4 hi-end-Mac.
I would guess more multi-CPU is not too likely but another significant step in Mhz could be possible.
Maybe even the smallest G4 Power Mac will be over 1 Ghz early next year.
If not I`d of course also be happy with the introduction of the G5

Comments
Alex
Having said that I'd love to see duals & quads offered, If Motorola has a large supply of G4's on hand and they try to unload them before the release of the G5. One can hope...
I was very close to buying one but opted for a dual PowerMac 9500 instead... what can I say.. I like the apple logo
imagine BeOS on a quad 604e... drool
[ 11-25-2001: Message edited by: macway ]</p>
word :cool:
<strong>I thought the current G4 wasn't fully MERSI compliant and thus could only go 2-way MP and not 4-way. Can someone verify this? (maybe this is why we saw a silent update by Motorola... fully MERSI compliant now?)</strong><hr></blockquote>
I think the fully MERSI compliant only matters in configs of 8 or more or something like that.
I think the bigger problems are
1.) bus
2.) the need
3.) the price
4.) the market
5.) r/d costs
MESI (7450, 604) compliance leaves out a small but crucial bit that the CPUs use to ensure cache coherence between them (in short, that they're all working with the same, current data: otherwise, one processor might have an older value for a given variable than another one). That omission limits the number of symmetric processors to 2 before support logic is needed..
MEI (603, 750) compliance means that support logic is required for any kind of SMP.