i belive the new power macs will have two dual core intel chips with hyper threading to make "8" processors for the OS
Charliehorse huh? Name sounds painful.
I also believe the future Powermacs in 2007 will have dual dual-core Intels. However you won't likely see them have HT because they're based off of cores that have about 15 pipelines. HT helps utilize core efficiently when it has more like 25+ pipelines.
I expect that HT will eventually be added back in but now that Intel is moving back down to under 20 pipeline stages the need for HT goes away. While HT is nice it doesn't beat having more registers and execution units.
I also believe the future Powermacs in 2007 will have dual dual-core Intels. However you won't likely see them have HT because they're based off of cores that have about 15 pipelines. HT helps utilize core efficiently when it has more like 25+ pipelines.
I expect that HT will eventually be added back in but now that Intel is moving back down to under 20 pipeline stages the need for HT goes away. While HT is nice it doesn't beat having more registers and execution units.
I just edited my answer.
Like you Hmurchinson I believed that HT will not help on small pipelined chips. But I just discover that the newcoming merom will have HT dispite it's 14 stage pipeline :
I also believe the future Powermacs in 2007 will have dual dual-core Intels. However you won't likely see them have HT because they're based off of cores that have about 15 pipelines. HT helps utilize core efficiently when it has more like 25+ pipelines.
I expect that HT will eventually be added back in but now that Intel is moving back down to under 20 pipeline stages the need for HT goes away. While HT is nice it doesn't beat having more registers and execution units.
Hmmmm,
I think you will find that HT is not about pipeline stages but the increasing gap between processor bandwidth demands and the ability of the memory system to supply it.
A processor thread is executing and requires data from main memory, which can take hundreds of processor cycles (not pipeline stages). The thread stalls and another thread is scheduled to execute until the first thread is ready to go. So pipeline stages is irrelevant. The need for hardware threads will increase until someone can get the memory system to increase in performance at the same or, hopefully, better rate than the processor.
Note that Sun is working on eight threads per core systems now to be released soon, it is a direction that others are following.
We are also going to see smaller, simpler cores. The small size allows them to run at higher clock rates without huge heat profiles (look at the SPEs on the Cell). Since chips are still going toward many hundreds of millions of transistors at 65nm, that means we are going to see lots of cores. Imagine a 500 million transistor chip filled with 20 million transistor cores... up to 25 of them... at 4+ GHz clock rates.
[B]Like you Hmurchinson I believed that HT will not help on small pipelined chips. But I just discover that the newcoming merom will have HT dispite it's 14 stage pipeline :
link
Quote:
"referring to technologies like Hyper-Threading and Virtualization"
I think that came from the editor Anton Shilov not from Pat Gelsinger.
Did anybody read the article on DigiTimes (membership needed)?
Quote:
"An important point is that Merom will be compatible with mobile platforms designed for Intel Pentium M processor based on the Yonah core."
Confirmed!
PowerBooks will use Yonah first and then switch to Merom
I think you will find that HT is not about pipeline stages but the increasing gap between processor bandwidth demands and the ability of the memory system to supply it.,
No this is incorrect. Hyperthreading and most forms of simultaneous multithreading do not involve the memory subsystem outside of the process. It is a feature that allows a processors unused execution units to be taken advantage of. From Wiki
Where execution resources in a non-Hyper-Threading capable processor are not used by the current task, and especially when the processor is stalled, a Hyper-Threading equipped processor may use those execution resources to execute the other scheduled task. (Reasons for the processor to stall include a cache miss, a branch misprediction and waiting for results of previous instructions before the current one can be executed.)
Basically in layman terms this means that a task is completed by the execution unit and thus the execution unit is now idle. SMT allows the cpu to take another task that must run through the execution unit and inert it. The reason why I mention pipeline stages is simply because when you have a long pipeline stage the process of moving the tasks through the longer pipeline is longer thus the execution units can remain idle longer. Shorter pipelines won't have this same problem
Wiki
The future of Hyper-Threading is not bright. With Intel shifting its priority in processor design to energy efficiency and multi-core instead of single-core performance, Hyper-Threading seems to be a dead end. Hyper-Threading consumes about the same amount of power as an additional processor core, even though adding the technology only offers a fraction of the performance increase compared to adding another core to a processor. Thus, Intel has decided to relegate Hyper-Threading to a feature used to separate top of the line enthusiast processors from mainstream processors. This is demonstrated in the difference between the mainstream Pentium D which does not support Hyper-Threading and the top of the line Pentium Extreme Edition which does support Hyper-Threading.
This is also evidenced by the lack of support for HT in the Pentium M and in the future Merom core based CPU.
Wiki quotes notwithstanding, I think you will find that HyperThreading (or Simultaneous Multi-Threading as "other" companies call it) will be motivated by what JRG suggests: memory/bus latencies continue to increase as processor clock rates improve. Pipeline depths will also increase. This will provide plenty of opportunity for multiple threads within a single core.
Actually, hmurchison, Intel unless xbit and hardmac reported incorrectly, Intel has just said that Merom would in fact integrate HyperThreading. Regarding latencies, I imagine that the cache-sharing CPUs will gain a fair amount from hyperthreading. It's much more likely that they will be dealing with data coming from both low and high latency sources at the same time.
Comments
HT doesnt splice processors.
Originally posted by charliehorse
i belive the new power macs will have two dual core intel chips with hyper threading to make "8" processors for the OS
Charliehorse huh? Name sounds painful.
I also believe the future Powermacs in 2007 will have dual dual-core Intels. However you won't likely see them have HT because they're based off of cores that have about 15 pipelines. HT helps utilize core efficiently when it has more like 25+ pipelines.
I expect that HT will eventually be added back in but now that Intel is moving back down to under 20 pipeline stages the need for HT goes away. While HT is nice it doesn't beat having more registers and execution units.
Originally posted by hmurchison
Charliehorse huh? Name sounds painful.
I also believe the future Powermacs in 2007 will have dual dual-core Intels. However you won't likely see them have HT because they're based off of cores that have about 15 pipelines. HT helps utilize core efficiently when it has more like 25+ pipelines.
I expect that HT will eventually be added back in but now that Intel is moving back down to under 20 pipeline stages the need for HT goes away. While HT is nice it doesn't beat having more registers and execution units.
I just edited my answer.
Like you Hmurchinson I believed that HT will not help on small pipelined chips. But I just discover that the newcoming merom will have HT dispite it's 14 stage pipeline :
link
Originally posted by hmurchison
Charliehorse huh? Name sounds painful.
I also believe the future Powermacs in 2007 will have dual dual-core Intels. However you won't likely see them have HT because they're based off of cores that have about 15 pipelines. HT helps utilize core efficiently when it has more like 25+ pipelines.
I expect that HT will eventually be added back in but now that Intel is moving back down to under 20 pipeline stages the need for HT goes away. While HT is nice it doesn't beat having more registers and execution units.
Hmmmm,
I think you will find that HT is not about pipeline stages but the increasing gap between processor bandwidth demands and the ability of the memory system to supply it.
A processor thread is executing and requires data from main memory, which can take hundreds of processor cycles (not pipeline stages). The thread stalls and another thread is scheduled to execute until the first thread is ready to go. So pipeline stages is irrelevant. The need for hardware threads will increase until someone can get the memory system to increase in performance at the same or, hopefully, better rate than the processor.
Note that Sun is working on eight threads per core systems now to be released soon, it is a direction that others are following.
Originally posted by Powerdoc
[B]Like you Hmurchinson I believed that HT will not help on small pipelined chips. But I just discover that the newcoming merom will have HT dispite it's 14 stage pipeline :
link
"referring to technologies like Hyper-Threading and Virtualization"
I think that came from the editor Anton Shilov not from Pat Gelsinger.
Did anybody read the article on DigiTimes (membership needed)?
"An important point is that Merom will be compatible with mobile platforms designed for Intel Pentium M processor based on the Yonah core."
Confirmed!
PowerBooks will use Yonah first and then switch to Merom
Hmmmm,
I think you will find that HT is not about pipeline stages but the increasing gap between processor bandwidth demands and the ability of the memory system to supply it.,
No this is incorrect. Hyperthreading and most forms of simultaneous multithreading do not involve the memory subsystem outside of the process. It is a feature that allows a processors unused execution units to be taken advantage of. From Wiki
Where execution resources in a non-Hyper-Threading capable processor are not used by the current task, and especially when the processor is stalled, a Hyper-Threading equipped processor may use those execution resources to execute the other scheduled task. (Reasons for the processor to stall include a cache miss, a branch misprediction and waiting for results of previous instructions before the current one can be executed.)
Basically in layman terms this means that a task is completed by the execution unit and thus the execution unit is now idle. SMT allows the cpu to take another task that must run through the execution unit and inert it. The reason why I mention pipeline stages is simply because when you have a long pipeline stage the process of moving the tasks through the longer pipeline is longer thus the execution units can remain idle longer. Shorter pipelines won't have this same problem
Wiki
The future of Hyper-Threading is not bright. With Intel shifting its priority in processor design to energy efficiency and multi-core instead of single-core performance, Hyper-Threading seems to be a dead end. Hyper-Threading consumes about the same amount of power as an additional processor core, even though adding the technology only offers a fraction of the performance increase compared to adding another core to a processor. Thus, Intel has decided to relegate Hyper-Threading to a feature used to separate top of the line enthusiast processors from mainstream processors. This is demonstrated in the difference between the mainstream Pentium D which does not support Hyper-Threading and the top of the line Pentium Extreme Edition which does support Hyper-Threading.
This is also evidenced by the lack of support for HT in the Pentium M and in the future Merom core based CPU.
Originally posted by charliehorse
i belive the new power macs will have two dual core intel chips with hyper threading to make "8" processors for the OS
Are you like nuts??