I just read you on that other crazy thread about the G5 being canceled. My advise..........take your meds, lie down, and forget about spreading the BS for awhile. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
Dewdrops, to answer a few of your questions, its not that simple.
A single processor is not constantly saturating the bus. In fact I would wager that even a dual 1Ghz G4 under heavy load is not maxing the buses bandwidth. That's something you need to distinguish between, bandwidth and latency. Bandwidth is how big your pipe is, like 128-bits. Latency is how fast things get there, determined mainly by the Mhz speed of the. When processors need information very often they don't need a lot of it, just a few memory addresses or something. But, processors DO want it fast, which is why we see a lot of things like the RAMBUS memory bus which is a much higher Mhz, but it also much narrower. So maybe a RAMBUS memory bus can only deliver 1/4 as much per clock cycle, but has 8 times the number of clock cycles per second.
The short answer is, no, putting four processors on a 133Mhz bus is not like giving them each a 33Mhz bus. The problem will get exponentially worse as you add processors though, because as you add more there are more wasted cycles as a request for one 32-bit integer from memory takes just as long as the request for four of them (on a 128-bit bus).
As far as disk writes are concerned, a hard disk couldn't even keep up with a 66Mhz, 64-bit PCI bus.
<strong>In fact I would wager that even a dual 1Ghz G4 under heavy load is not maxing the buses bandwidth.</strong><hr></blockquote>
I'll take that wager... even the slowest G4 can grind through an astounding amount of data quite easily at its full memory bandwidth, even without using the AltiVec unit.
<strong>Dewdrops, to answer a few of your questions, its not that simple.
A single processor is not constantly saturating the bus. In fact I would wager that even a dual 1Ghz G4 under heavy load is not maxing the buses bandwidth. That's something you need to distinguish between, bandwidth and latency. Bandwidth is how big your pipe is, like 128-bits. Latency is how fast things get there, determined mainly by the Mhz speed of the. When processors need information very often they don't need a lot of it, just a few memory addresses or something. But, processors DO want it fast, which is why we see a lot of things like the RAMBUS memory bus which is a much higher Mhz, but it also much narrower. So maybe a RAMBUS memory bus can only deliver 1/4 as much per clock cycle, but has 8 times the number of clock cycles per second.
The short answer is, no, putting four processors on a 133Mhz bus is not like giving them each a 33Mhz bus. The problem will get exponentially worse as you add processors though, because as you add more there are more wasted cycles as a request for one 32-bit integer from memory takes just as long as the request for four of them (on a 128-bit bus).
As far as disk writes are concerned, a hard disk couldn't even keep up with a 66Mhz, 64-bit PCI bus.</strong><hr></blockquote>
Hold on there buddy, you're way off the mark here.
First, Rambus has much higher latency than both DDR and PC 133 but it has more bandwith than both and that's where its strength lies. In other words it's exactly the opposite of what you're claiming. Just 'cause RDRAM is only 16 bits and runs at 800 Mhz doesn't mean it's low latency and narrow bandwidth.
And yes 4 processors would absolutely choke a 133 Mhz bus and even 2 must definitely be choking it now.
Most importantly, the majority of applications where the performance of the computer in general and the memory in particular are important are things like video/multimedia, scientific calculations and 3D. These are usually more sensitive to bandwith than they are to latency, so as long as latency is not horrible, bandwith rules...
<strong>Heh, well if the G5 is not ready this summer then this level of public expectation is going to be making the guys at Apple and Motorola awfully nervous. AI Forums is one thing, Forbes is entirely different.</strong><hr></blockquote>
While I agree with the sentiment you expressed, keep in mind that this is forbes.com saying this, not Forbes the magazine. They also didn't say anything, other than "speculation is that the G5 will come out this summer" -- who knows where they got their speculation from? Likely all of the self-created rumours on The Register, in forums like these, etc.
I don't blame anyone for pining away for a G5 -- we'd all love Apple to make a quantum leap in processor power, and soon. But there is that nasty thing called reality...
Hmmm. Architosh have apparently published another G5 article, this one called Future G5 News: Test boxes, schedules and more.... According to macsurfer that is.
I haven't had any luck getting through. If you have, why not share with the rest of the us?
A lot of BS too. I personally think our arguments are as least as well founded as theirs.
Only thing they have we don't is publicity.
G-News</strong><hr></blockquote>
Agreed. In the age of the internet, even mainstream pubs have a hard time resisting poaching speculation from less savory (i.e. us) sources. Say something often enough and people take notice...
While I agree with the sentiment you expressed, keep in mind that this is forbes.com saying this, not Forbes the magazine.
</strong><hr></blockquote>
If this is a factor then its disturbing that online news services seem to feel that its okay to let their journalistic standards be more lax than in the printed media. I don't read Forbes or forbes.com so I don't know if it holds for them.
[quote]<strong>
They also didn't say anything, other than "speculation is that the G5 will come out this summer" -- who knows where they got their speculation from? Likely all of the self-created rumours on The Register, in forums like these, etc.
</strong><hr></blockquote>
True. On the subject of The Register though, they normally don't seem to be indulging in "self-created rumours"... perhaps you have some evidence for it, but I don't. And when they speculate they're usually clear about it. They are just collecting emails that anybody could have sent, so spoofing them wouldn't be terribly hard. Looking over their G5 rumours going back a year, they imply having numerous sources (i.e. email addresses in the "from" field) which means it would have to be a sustained effort at spoofing them. Possible, but likely?
<strong> [quote]I don't blame anyone for pining away for a G5 -- we'd all love Apple to make a quantum leap in processor power, and soon. But there is that nasty thing called reality...</strong><hr></blockquote>
True... but just because you don't see it doesn't mean it isn't happening. I (and most people on AI) don't have any conduits of information about this stuff, aside from what we read on the rumour sites. If there were a tightly lidded skunkworks project going on, rumour sites are where we'd hear about it. It has happened before.
In your case, you seem to be used to hearing about it 2nd hand from people you know... but if that was identified as a known security leak and cut off, then you wouldn't know the difference, would you? Especially if the Apollo project wasn't put under the same lid and so you heard about that as usual. Yeah, I know... it seems like a stretch, but it is possible.
The mythical G5 wouldn't come out of thin air, and there is nothing unrealistic about a tight, very focussed development team working feverishly on a project in some back room and not leaking any information about it to the outside world. I've seen it happen at my company (in retrospect, of course, since I didn't know it was there until it went "public"). Its past would no doubt be rooted in the Core 2K project that started at Somerset, and/or work done at Motorola. Its existance wouldn't start leaking until people outside the core team started to have to see it -- people at fabs, people in testing, etc. And, strangely, that's where most of the supposed rumours are from.
There are lots of reasons to believe that this could be true, even aside from the rumours (and the often silly "reasoning" displayed on AI forums). I started listing them, but why bother? We've all seen them repeatedly. I think everybody now accepts that the new PowerMacs will last us at least until either WWDC or MWNY. After that it is only a matter of time until the next processor Apple will use, and I don't think anybody argues that Apple will never have another processor. So the argument boils down to a +/- 6 month window centered roughly on MWSF next year (with extreme optimists and pessimists being outside of that window).
As for the performance of the chip, there is no inherent reason why a completely new design won't be on par with x86 chips in the same time frame... and the cleaner design of the PPC ISA (less legacy baggage) gives some hope that it will be better. The main issue will be which fab technology it uses, but there are many advanced foundries to choose from so severing the ties to Motorola's questionable foundries may be a good thing.
Hold on there buddy, you're way off the mark here.
First, Rambus has much higher latency than both DDR and PC 133 but it has more bandwith than both and that's where its strength lies. In other words it's exactly the opposite of what you're claiming. Just 'cause RDRAM is only 16 bits and runs at 800 Mhz doesn't mean it's low latency and narrow bandwidth.
And yes 4 processors would absolutely choke a 133 Mhz bus and even 2 must definitely be choking it now.
Most importantly, the majority of applications where the performance of the computer in general and the memory in particular are important are things like video/multimedia, scientific calculations and 3D. These are usually more sensitive to bandwith than they are to latency, so as long as latency is not horrible, bandwith rules...
The memory bandwith of the mac is not very good that's why Motorola and Apple choose a different way, they make a very efficient L3 cache with DDR ram with a memory bandwitch up to 4 GByte per second.
An hard question here : what is the most performant in general : sdram 133 mhz with very performant L3 cache or ddr ram 133 mhz *2 without L3 cache ?
Timmortis, when you refer to latency I believe you are speaking about the actual reponse time of the memory itself. I am talking about the time it takes the data to flow over the bus once retrieved from memory.
<strong>Timmortis, when you refer to latency I believe you are speaking about the actual reponse time of the memory itself. I am talking about the time it takes the data to flow over the bus once retrieved from memory.</strong><hr></blockquote>
From the processor's point of view the two are indistinguishable. The processor only cares about how long after it asks for a piece of data that it appears (which includes the memory response time and the bus transmission time).
Comments
I just read you on that other crazy thread about the G5 being canceled. My advise..........take your meds, lie down, and forget about spreading the BS for awhile. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
A single processor is not constantly saturating the bus. In fact I would wager that even a dual 1Ghz G4 under heavy load is not maxing the buses bandwidth. That's something you need to distinguish between, bandwidth and latency. Bandwidth is how big your pipe is, like 128-bits. Latency is how fast things get there, determined mainly by the Mhz speed of the. When processors need information very often they don't need a lot of it, just a few memory addresses or something. But, processors DO want it fast, which is why we see a lot of things like the RAMBUS memory bus which is a much higher Mhz, but it also much narrower. So maybe a RAMBUS memory bus can only deliver 1/4 as much per clock cycle, but has 8 times the number of clock cycles per second.
The short answer is, no, putting four processors on a 133Mhz bus is not like giving them each a 33Mhz bus. The problem will get exponentially worse as you add processors though, because as you add more there are more wasted cycles as a request for one 32-bit integer from memory takes just as long as the request for four of them (on a 128-bit bus).
As far as disk writes are concerned, a hard disk couldn't even keep up with a 66Mhz, 64-bit PCI bus.
<strong>In fact I would wager that even a dual 1Ghz G4 under heavy load is not maxing the buses bandwidth.</strong><hr></blockquote>
I'll take that wager... even the slowest G4 can grind through an astounding amount of data quite easily at its full memory bandwidth, even without using the AltiVec unit.
<strong>Dewdrops, to answer a few of your questions, its not that simple.
A single processor is not constantly saturating the bus. In fact I would wager that even a dual 1Ghz G4 under heavy load is not maxing the buses bandwidth. That's something you need to distinguish between, bandwidth and latency. Bandwidth is how big your pipe is, like 128-bits. Latency is how fast things get there, determined mainly by the Mhz speed of the. When processors need information very often they don't need a lot of it, just a few memory addresses or something. But, processors DO want it fast, which is why we see a lot of things like the RAMBUS memory bus which is a much higher Mhz, but it also much narrower. So maybe a RAMBUS memory bus can only deliver 1/4 as much per clock cycle, but has 8 times the number of clock cycles per second.
The short answer is, no, putting four processors on a 133Mhz bus is not like giving them each a 33Mhz bus. The problem will get exponentially worse as you add processors though, because as you add more there are more wasted cycles as a request for one 32-bit integer from memory takes just as long as the request for four of them (on a 128-bit bus).
As far as disk writes are concerned, a hard disk couldn't even keep up with a 66Mhz, 64-bit PCI bus.</strong><hr></blockquote>
Hold on there buddy, you're way off the mark here.
First, Rambus has much higher latency than both DDR and PC 133 but it has more bandwith than both and that's where its strength lies. In other words it's exactly the opposite of what you're claiming. Just 'cause RDRAM is only 16 bits and runs at 800 Mhz doesn't mean it's low latency and narrow bandwidth.
And yes 4 processors would absolutely choke a 133 Mhz bus and even 2 must definitely be choking it now.
Most importantly, the majority of applications where the performance of the computer in general and the memory in particular are important are things like video/multimedia, scientific calculations and 3D. These are usually more sensitive to bandwith than they are to latency, so as long as latency is not horrible, bandwith rules...
For your reference :
dual channel PC800 RDRAM (as in p4) = 3.2 GB/s
PC 2100 DDR = 2.1 GB/s
[ 02-01-2002: Message edited by: timortis ]</p>
<strong>Heh, well if the G5 is not ready this summer then this level of public expectation is going to be making the guys at Apple and Motorola awfully nervous. AI Forums is one thing, Forbes is entirely different.</strong><hr></blockquote>
While I agree with the sentiment you expressed, keep in mind that this is forbes.com saying this, not Forbes the magazine. They also didn't say anything, other than "speculation is that the G5 will come out this summer" -- who knows where they got their speculation from? Likely all of the self-created rumours on The Register, in forums like these, etc.
I don't blame anyone for pining away for a G5 -- we'd all love Apple to make a quantum leap in processor power, and soon. But there is that nasty thing called reality...
Hmmm. Architosh have apparently published another G5 article, this one called Future G5 News: Test boxes, schedules and more.... According to macsurfer that is.
I haven't had any luck getting through. If you have, why not share with the rest of the us?
<strong>Forbes has been saying a lot in the past.
A lot of BS too. I personally think our arguments are as least as well founded as theirs.
Only thing they have we don't is publicity.
G-News</strong><hr></blockquote>
Agreed. In the age of the internet, even mainstream pubs have a hard time resisting poaching speculation from less savory (i.e. us) sources. Say something often enough and people take notice...
Caler
<strong>
While I agree with the sentiment you expressed, keep in mind that this is forbes.com saying this, not Forbes the magazine.
</strong><hr></blockquote>
If this is a factor then its disturbing that online news services seem to feel that its okay to let their journalistic standards be more lax than in the printed media. I don't read Forbes or forbes.com so I don't know if it holds for them.
[quote]<strong>
They also didn't say anything, other than "speculation is that the G5 will come out this summer" -- who knows where they got their speculation from? Likely all of the self-created rumours on The Register, in forums like these, etc.
</strong><hr></blockquote>
True. On the subject of The Register though, they normally don't seem to be indulging in "self-created rumours"... perhaps you have some evidence for it, but I don't. And when they speculate they're usually clear about it. They are just collecting emails that anybody could have sent, so spoofing them wouldn't be terribly hard. Looking over their G5 rumours going back a year, they imply having numerous sources (i.e. email addresses in the "from" field) which means it would have to be a sustained effort at spoofing them. Possible, but likely?
<strong> [quote]I don't blame anyone for pining away for a G5 -- we'd all love Apple to make a quantum leap in processor power, and soon. But there is that nasty thing called reality...</strong><hr></blockquote>
True... but just because you don't see it doesn't mean it isn't happening. I (and most people on AI) don't have any conduits of information about this stuff, aside from what we read on the rumour sites. If there were a tightly lidded skunkworks project going on, rumour sites are where we'd hear about it. It has happened before.
In your case, you seem to be used to hearing about it 2nd hand from people you know... but if that was identified as a known security leak and cut off, then you wouldn't know the difference, would you? Especially if the Apollo project wasn't put under the same lid and so you heard about that as usual. Yeah, I know... it seems like a stretch, but it is possible.
The mythical G5 wouldn't come out of thin air, and there is nothing unrealistic about a tight, very focussed development team working feverishly on a project in some back room and not leaking any information about it to the outside world. I've seen it happen at my company (in retrospect, of course, since I didn't know it was there until it went "public"). Its past would no doubt be rooted in the Core 2K project that started at Somerset, and/or work done at Motorola. Its existance wouldn't start leaking until people outside the core team started to have to see it -- people at fabs, people in testing, etc. And, strangely, that's where most of the supposed rumours are from.
There are lots of reasons to believe that this could be true, even aside from the rumours (and the often silly "reasoning" displayed on AI forums). I started listing them, but why bother? We've all seen them repeatedly. I think everybody now accepts that the new PowerMacs will last us at least until either WWDC or MWNY. After that it is only a matter of time until the next processor Apple will use, and I don't think anybody argues that Apple will never have another processor. So the argument boils down to a +/- 6 month window centered roughly on MWSF next year (with extreme optimists and pessimists being outside of that window).
As for the performance of the chip, there is no inherent reason why a completely new design won't be on par with x86 chips in the same time frame... and the cleaner design of the PPC ISA (less legacy baggage) gives some hope that it will be better. The main issue will be which fab technology it uses, but there are many advanced foundries to choose from so severing the ties to Motorola's questionable foundries may be a good thing.
So have I said anything unreasonable here, Moki?
<strong>
Hold on there buddy, you're way off the mark here.
First, Rambus has much higher latency than both DDR and PC 133 but it has more bandwith than both and that's where its strength lies. In other words it's exactly the opposite of what you're claiming. Just 'cause RDRAM is only 16 bits and runs at 800 Mhz doesn't mean it's low latency and narrow bandwidth.
And yes 4 processors would absolutely choke a 133 Mhz bus and even 2 must definitely be choking it now.
Most importantly, the majority of applications where the performance of the computer in general and the memory in particular are important are things like video/multimedia, scientific calculations and 3D. These are usually more sensitive to bandwith than they are to latency, so as long as latency is not horrible, bandwith rules...
For your reference :
dual channel PC800 RDRAM (as in p4) = 3.2 GB/s
PC 2100 DDR = 2.1 GB/s
[ 02-01-2002: Message edited by: timortis ]</strong><hr></blockquote>
The memory bandwith of the mac is not very good that's why Motorola and Apple choose a different way, they make a very efficient L3 cache with DDR ram with a memory bandwitch up to 4 GByte per second.
An hard question here : what is the most performant in general : sdram 133 mhz with very performant L3 cache or ddr ram 133 mhz *2 without L3 cache ?
Perhaps only apple engineers have an answer ...
<strong>
An hard question here : what is the most performant in general : sdram 133 mhz with very performant L3 cache or ddr ram 133 mhz *2 without L3 cache ?
Perhaps only apple engineers have an answer ...</strong><hr></blockquote>
Depends a lot on what you plan to do.
For transient data (DSP type stuff), caches are completely useless as items of data tend to not get re-used at all.
On the other hand, programs that have working sets smaller than 2MB can get a huge performance improvement over DDR w/o L3.
So, it all depends on the app in question.
Bye,
RazzFazz
<strong>Timmortis, when you refer to latency I believe you are speaking about the actual reponse time of the memory itself. I am talking about the time it takes the data to flow over the bus once retrieved from memory.</strong><hr></blockquote>
From the processor's point of view the two are indistinguishable. The processor only cares about how long after it asks for a piece of data that it appears (which includes the memory response time and the bus transmission time).