There are a whole pile of PC chipsets to choose from, and there are remarkable performance differences between them even with the same kind of memory. Several of them deliver substantially better performance than the Apple chipset is even theoretically capable of. The Apple chipset delivers remarkably close to the theoretical memory speed these days, but it is still well behind the good PC DDR & RAMBus chipsets. By no stretch of the imagination can it be considered three times as fast!
It also doesn't use a "special kind of RAM", do any bank interleaving, or anything else mystical to somehow beat the PC. This is just wishful thinking... and even if Apple built a super memory subsystem, it still couldn't push data into the processor any faster because of the 64-bit MPX bus on the current processors. I really hope the next processor corrects this problem, but for that we have to wait for the next processor.
<strong>By no stretch of the imagination can it be considered three times as fast!
It also doesn't use a "special kind of RAM", do any bank interleaving, or anything else mystical to somehow beat the PC.
</strong><hr></blockquote>
Oops, guess my reply was kinda misunderstandable.
I was just trying to say that something like "two brains are better than one" in regard to memory could well be possible in future hardware designs by use of memory bank interleaving (and it is already true for dual channel rambus systems).
I never intended to say Apple did any of this in their current lineup, and sure of course it wouldn't give a 3x speed increase either, it just fits the "two brains" analogy.
<strong>Would memory bank interleaving have the same bandwidth as DDR-SDRAM? Say 4 slots that you upgrade 2 at a time.
</strong><hr></blockquote>
Yes, that's the point of doing it.
[quote]<strong>It still doesn't solve the bandwith to CPU problem though, unless MPX supports 128bit in the 745X series and i think it only has 64 bit support in those processors.</strong><hr></blockquote>
Of course. As stated above, I wasn't trying to say that interleaving was done on current hardware, and sure as hell beefing up the FSB would be a prerequisite to use it.
[quote]<strong>But the spec is there to make 128bit MPX.</strong><hr></blockquote>
I read that several times now, but only on rumour sites - does anyone have a link that proves this is more than a rumour?
<strong>It also doesn't use a "special kind of RAM", do any bank interleaving, or anything else mystical to somehow beat the PC. This is just wishful thinking... and even if Apple built a super memory subsystem, it still couldn't push data into the processor any faster because of the 64-bit MPX bus on the current processors. I really hope the next processor corrects this problem, but for that we have to wait for the next processor.</strong><hr></blockquote>
OTOH, Apple could go to "dual channel" SDRAM, with each bank feeding half of the 128-bit variant of the MPX bus... but what are the odds?
Neither would I. Say what you want about rambus the company but the technology is sound. One you get past the initial latency it's very fast and on par with DDR pricing now.
<strong>Neither would I. Say what you want about rambus the company but the technology is sound. One you get past the initial latency it's very fast and on par with DDR pricing now.</strong><hr></blockquote>
The rambus technology is now nature, it was not in the beginning , but it's still more expansive than DDR ram (in France , i don't know the prize of the US market).
Rambus also, is not a standart, you can bet you will see Apple jump drectly to Quaddata rate ram. 133 mhz *4 equal 533 mhz : isn't it impressive ?
Does it absolutely have to be that way, or it that just how Apple happens to be doing it now?</strong><hr></blockquote>
That's how the G4 and MaxBus were designed to work.
You might be able to give every processor his own individual front side bus (by means of a northbridge with two separate MaxBuses), but this would basically be nothing short of a hack, very difficult to implement, and most likely completely infeasible. Infact, it would probably be even slower than the current, shared bus architecture, because of lack of support for cache coherency and snooping across the buses. Thus, you'd have to go through main memory instead, and that's orders of magnitude slower.
Comments
It also doesn't use a "special kind of RAM", do any bank interleaving, or anything else mystical to somehow beat the PC. This is just wishful thinking... and even if Apple built a super memory subsystem, it still couldn't push data into the processor any faster because of the 64-bit MPX bus on the current processors. I really hope the next processor corrects this problem, but for that we have to wait for the next processor.
<strong>By no stretch of the imagination can it be considered three times as fast!
It also doesn't use a "special kind of RAM", do any bank interleaving, or anything else mystical to somehow beat the PC.
</strong><hr></blockquote>
Oops, guess my reply was kinda misunderstandable.
I was just trying to say that something like "two brains are better than one" in regard to memory could well be possible in future hardware designs by use of memory bank interleaving (and it is already true for dual channel rambus systems).
I never intended to say Apple did any of this in their current lineup, and sure of course it wouldn't give a 3x speed increase either, it just fits the "two brains" analogy.
Bye,
RazzFazz
<strong>Would memory bank interleaving have the same bandwidth as DDR-SDRAM? Say 4 slots that you upgrade 2 at a time.
</strong><hr></blockquote>
Yes, that's the point of doing it.
[quote]<strong>It still doesn't solve the bandwith to CPU problem though, unless MPX supports 128bit in the 745X series and i think it only has 64 bit support in those processors.</strong><hr></blockquote>
Of course. As stated above, I wasn't trying to say that interleaving was done on current hardware, and sure as hell beefing up the FSB would be a prerequisite to use it.
[quote]<strong>But the spec is there to make 128bit MPX.</strong><hr></blockquote>
I read that several times now, but only on rumour sites - does anyone have a link that proves this is more than a rumour?
Bye,
RazzFazz
<strong>It also doesn't use a "special kind of RAM", do any bank interleaving, or anything else mystical to somehow beat the PC. This is just wishful thinking... and even if Apple built a super memory subsystem, it still couldn't push data into the processor any faster because of the 64-bit MPX bus on the current processors. I really hope the next processor corrects this problem, but for that we have to wait for the next processor.</strong><hr></blockquote>
OTOH, Apple could go to "dual channel" SDRAM, with each bank feeding half of the 128-bit variant of the MPX bus... but what are the odds?
DDR II <a href="http://www.ebnews.com/digest/story/OEG20010625S0104"; target="_blank">looks promising</a>, but it also looks like it's not coming to 2003.
Hmm.
That dovetails with some estimates for the ETA of the G5. And the G5 has been rumored to ship with a 400MHz (effective) bus - DDR II starts at 400MHz.
Food for thought, I suppose.
[ 02-05-2002: Message edited by: Amorph ]</p>
<strong>
OTOH, Apple could go to "dual channel" SDRAM, with each bank feeding half of the 128-bit variant of the MPX bus... but what are the odds?
</strong><hr></blockquote>
Well, depends on whether you can find a G4 somewhere that actually supports 128 data lines...
Bye,
RazzFazz
<strong>Neither would I. Say what you want about rambus the company but the technology is sound. One you get past the initial latency it's very fast and on par with DDR pricing now.</strong><hr></blockquote>
The rambus technology is now nature, it was not in the beginning , but it's still more expansive than DDR ram (in France , i don't know the prize of the US market).
Rambus also, is not a standart, you can bet you will see Apple jump drectly to Quaddata rate ram. 133 mhz *4 equal 533 mhz : isn't it impressive ?
<strong>
Heh, where'd you get that crap? Its total bunk.</strong><hr></blockquote>
Take it easy, JD was just being sarcastic. He's just spoofing the total bunk that's "the megahertz myth" the way Apple presents it.
<strong>
Well, depends on whether you can find a G4 somewhere that actually supports 128 data lines...
Bye,
RazzFazz</strong><hr></blockquote>
Would a dual G4 count?
<strong>
Would a dual G4 count?</strong><hr></blockquote>
No, 'cos there's only one 133MHz 64bit MaxBus connecting the processor module to UniNorth, which is shared by both processors.
Bye,
RazzFazz
<strong>
No, 'cos there's only one 133MHz 64bit MaxBus connecting the processor module to UniNorth, which is shared by both processors.
Bye,
RazzFazz</strong><hr></blockquote>
Does it absolutely have to be that way, or it that just how Apple happens to be doing it now?
<strong>
Does it absolutely have to be that way, or it that just how Apple happens to be doing it now?</strong><hr></blockquote>
That's how the G4 and MaxBus were designed to work.
You might be able to give every processor his own individual front side bus (by means of a northbridge with two separate MaxBuses), but this would basically be nothing short of a hack, very difficult to implement, and most likely completely infeasible. Infact, it would probably be even slower than the current, shared bus architecture, because of lack of support for cache coherency and snooping across the buses. Thus, you'd have to go through main memory instead, and that's orders of magnitude slower.
Bye,
RazzFazz
[ 02-07-2002: Message edited by: RazzFazz ]</p>