AltiVec implementation in the PPC G5

2

Comments

  • Reply 21 of 51
    Well, after countless off-topic posts, I figure I'll chime in on the G5. Apparently (according to rumour) the first generation will have regular Altivec, and the follow-up revision will have 256-bit Altivec 2.



    But seriously, unless some magical flying monkeys deliver motherboards with modern bus speeds, there's not much point to Alt 2.



    The instructions and data won't get to the processor fast enough to make a tangible difference.



    Come, you flying monkeys... Hurry!!!!



    *scree!! SCREEEE!!!!*



    [ 02-25-2002: Message edited by: stimuli ]</p>
  • Reply 22 of 51
    [quote]Originally posted by stimuli:

    <strong>Dartblazer, on what basis do you think rambus is better than DDR? I've yet to see a rambus based machine perform at all amazing, and considering it costs the earth, what are the benefits?



    You do realize, that although it runs at say 400mhz, it is 16 bit? And that my laptop has (ie) 64bit ram?



    Besides low latency (getting the data to the processor at first), it has no real performance advantage?</strong><hr></blockquote>



    RDRAM has a high latency and high throughput (compared to DDR). This is a good match to the Pentium 4 as it needs a high throughput. The G4 has proven to be far less bound to a slow bus (see the incredible high performance that the dual 1Ghz Mac can achieve on a 133Mhz bus). This indicates that low latencies are far more important and DDR-DRAM will achieve better results.



    So DDR is indeed a better choice, but your reasoning is flawed.
  • Reply 23 of 51
    telomartelomar Posts: 1,804member
    If we are going to get to discussing RDRAM, DDR-SDRAM, the P IV and higher bus speeds I would read this:



    <a href="http://www.tomshardware.com/cpu/02q1/020225/index.html"; target="_blank">read me</a>



    All the current memory options have constraints and benefits. RDRAM would not be the best option for current powermacs or those that will appear for a while yet though.



    I should mention this can't be taken as perfect since it compares tomorrow's PIVs to today's tech. Clearly that is going to favour the PIVs a little. However just look at some of the trends with performance, etc.



    [ 02-25-2002: Message edited by: Telomar ]</p>
  • Reply 24 of 51
    onlookeronlooker Posts: 5,252member
    I would like to know where in world you all heard this about the G5, and Altivec, because as of two weeks ago (the last time I looked at motorolas PPC roadmap) There was no Altivec planned for the G5. Which is what I have been complaining about forever. Without Altivec we are just dealing with another processor that rely's mostly on MHz to perform if you ask me.



    If there is real evidence from motorola that the G5 will have Altivec please show it to me.



    ONE LAST THING. PLEASE REMOVE THAT GRAPHIC ABOVE THIS PAGE TAKES FOREVER TO LOAD WITHOUT HIGHER BANDWIDTH AND WHEN THERE ARE MANY PEOPLE HERE IT DOES NOT LOAD AT ALL. THANK YOU



    [ 02-25-2002: Message edited by: onlooker ]</p>
  • Reply 25 of 51
    msleemslee Posts: 143member
    Oh, I'm sorry, would you care to link to the Motorola G5 roadmap where it magically details Motorola's plans for the processr?
  • Reply 26 of 51
    The roadmap does not say that there's no Atlivec unit on the G5.



    Maybe it just doesn't list Altivec under the G5, since that is an innovation that took place with the G4, and they only list the new features of each successive processor on the roadmap.



    &lt;rant&gt;Why is this possibility so incredibly difficult for many people to consider?&lt;/rant&gt;



    [ 02-25-2002: Message edited by: Bozo the Clown ]</p>
  • Reply 27 of 51
    Dangit, i just looked at MOT's ppc roadmap, and guess what the G5 isn't going to have L1 or L2 cache at all, according to the roadmap at least. Dumbasses, just because the crappy roadmap doesnt have altivec listed doesn't mean it wont be there.
  • Reply 28 of 51
    moogsmoogs Posts: 4,296member
    Repeat after me...



    "Roadmaps" from CPU manufacturers are NOT reliable indicators of future CPU parts. They are MARKETING FLUFF.



    OK. Once more now, with feeling....
  • Reply 29 of 51
    after me. "Roadmaps" from CPU manufacturers are NOT reliable indicators of future CPU parts. They are MARKETING FLUFF. OK. Once more now, with feeling....



    hehe



    but seriously we shouldnt be concerned about whether or not the G5 is going to support this or that, we should worry about when in the hell it will be here.
  • Reply 30 of 51
    My personal feeling is this with the roadmap is why list everything.



    Every CPU for a desktop computer has a SIMD, why wouldn't this one? Do we need to list everything they plan on doing with this chip?
  • Reply 31 of 51
    powerdocpowerdoc Posts: 8,123member
    You can bet that the G5 will work with DDR or QDR ram and not Rambus. Why because despite the technical aspects of this. there is two importants points :

    - the minor one, Rambus is more expansive than DDR.

    - the major point, Rambus is an Intel technology. I doubt that motorola will use it.
  • Reply 32 of 51
    outsideroutsider Posts: 6,008member
    According to Rambus, DDR is also a Rambus technology So either way we're screwed.
  • Reply 33 of 51
    mattyjmattyj Posts: 898member
    Originally posted by Tomahawk:

    [quote] No, then they could say they have a Gamer's Mac. As long as the PowerMac is fast for Photoshop, other graphics programs, video, and runs all your office software it can be called a PowerMac. <hr></blockquote>



    This is not what I am getting at. A game is so processor intensive that it is a very good indicator of performance.



    To prove it, I ask you this, what is more taxing on a G4, Quake 3, or running photoshop filters?? If you say the latter then you know nothing.



    Quake 3 does not blaze away on a mac as it does with PCs, but with the case of photoshop, this is not true, macs (G4s) are on a par.
  • Reply 34 of 51
    airslufairsluf Posts: 1,861member
  • Reply 35 of 51
    onlookeronlooker Posts: 5,252member
    Oops!



    [ 02-26-2002: Message edited by: onlooker ]</p>
  • Reply 36 of 51
    onlookeronlooker Posts: 5,252member
    [quote]Originally posted by mslee:

    <strong>Oh, I'm sorry, would you care to link to the Motorola G5 roadmap where it magically details Motorola's plans for the processr?</strong><hr></blockquote>





    [quote]Originally posted by onlooker:

    <strong>



    Hey it was in motorola's roadmap at mot.com before IBM had said they didn't plan to use Altvec in their version of the G5, as I recall, and that is why I'm saying it looks just like any other processor that's based on MHz to perform.



    So if your looking for a roadmap go to mot.com, and find it your self. Because after removing it (Altivec) from the G5 on their PPC roadmap I think it's their way of saying their not using it anymore. Ok. It's just how I'm interpeting the situation. Your free to draw your own conclusion from it. Unless of course your Canadian, and then your freedom is provided to you by us you freakin chanuk!

    </strong><hr></blockquote>



    [ 02-26-2002: Message edited by: onlooker ]</p>
  • Reply 37 of 51
    [quote]Originally posted by dartblazer:

    <strong>after me. "Roadmaps" from CPU manufacturers are NOT reliable indicators of future CPU parts. They are MARKETING FLUFF. OK. Once more now, with feeling....



    hehe



    but seriously we shouldnt be concerned about whether or not the G5 is going to support this or that, we should worry about when in the hell it will be here.</strong><hr></blockquote>



    july. not from motorola.
  • Reply 38 of 51
    Hey ada I like your short crisp answer but can you elaborate on how you know or if it is just a guess. if not well then mystery will prevail
  • Reply 39 of 51
    airslufairsluf Posts: 1,861member
  • Reply 40 of 51
    msleemslee Posts: 143member
    Apparently, some people here don't understand the nature of the Book E specification. Book E compliant -CPUs, by design and definition, are able to accept specific application-specific processing units (APUs). AltiVec, as you might imagine, is considered an APU under the Book E specification. Given that the G5 will be a Book E-compliant processor, adding the AltiVec APU should be possible. Given the large amount of AltiVec optimizations that have gone into the core Apple applications (like Photoshop, Illustrator, iTunes, FCP, iMovie, iDVD, DVD Studio Pro, BLAST, Freehand, GoLive, games, etc...) and even its OS (OS X' Quartz is optimized for the Velocity Engine), Apple would have to be run by serious monkey's to piss away an elegant solution for applications that require intense CPU activity.



    What is this bullshit about "someone else" delivering the next generation Gx chip? LOL! What a load of crap! Quite fankly, Motorola and IBM are about neck -and-neck when it comes to real breakthroughs in processor design. Motorola had a disasterous incident with the cache-coherency problem with the G4, and even more serious fab problems, but this doesn't preclude Motorola from taking the lead in CPU design again.



    Bah. In the end, who cares. As soon as Apple develops/implements a new memory controller that can properly feed two processors...I'm buying. I'm tempted so much by the new dual gigs I can barely stop myself. If you people really, really, really, want performance you can see and feel...get a RAID card and stripe two IBM 120GXPs or the massive-cached Caviar hard drives.
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