Damn, it's just insane the levels of miniaturization being achieved. I remember reading numerous articles a few years ago about the challenges and obstacles in silicon going down to this level. I wonder what they're doing to resolve the problem of physics and keeping those electrons going where they're supposed to go.
Somewhere out there is the next chapter of fabrication processes. Silicon is fast-becoming an obsolete material to use. What's next?
Well, just knowing where they are at that level is a challenge, cause the electrons position is a wave function and part of that electron is beyond the gate... Oh my.
Reducing the voltage and frequency I suppose reduces how much bleeds through but then you got some slow ass chip.
Accepting the bleed and finding a way to detect a less than ideal threshold can work. Also trying to better spread out the contact surface would help.
Didn't they try to wrap the gate (not just in a plane but in 3D) to alleviate this or am I thinking of something else entirely.
The Uncertainty Principle comes into play as well. As the trace shrinks toward atomic size, the electron’s position becomes more pinned down, thus it’s velocity becomes more uncertain, leading to strange quantum effects.
Maybe I’m overthinking this, but “scaled back” does not seem like the appropriate term when describing this technical achievement. Yes, I get that it is a smaller process.
Damn, it's just insane the levels of miniaturization being achieved. I remember reading numerous articles a few years ago about the challenges and obstacles in silicon going down to this level. I wonder what they're doing to resolve the problem of physics and keeping those electrons going where they're supposed to go.
Somewhere out there is the next chapter of fabrication processes. Silicon is fast-becoming an obsolete material to use. What's next?
Well, just knowing where they are at that level is a challenge, cause the electrons position is a wave function and part of that electron is beyond the gate... Oh my.
Reducing the voltage and frequency I suppose reduces how much bleeds through but then you got some slow ass chip.
Accepting the bleed and finding a way to detect a less than ideal threshold can work. Also trying to better spread out the contact surface would help.
Didn't they try to wrap the gate (not just in a plane but in 3D) to alleviate this or am I thinking of something else entirely.
The Uncertainty Principle comes into play as well. As the trace shrinks toward atomic size, the electron’s position becomes more pinned down, thus it’s velocity becomes more uncertain, leading to strange quantum effects.
Kinda linked to what I said; the electron's position is probabilistic, you know how much chance it has to be there, but that's doesn't mean its there!
The trace if just the place were its more likely it will be, they're trying to corral a wild horse at that level. It's half way out and in .
Tunneling has to do with the fact that at that level, everything has a particle-wave duality.
Having switches that are not just on or off, but exploits this "dimmer" nature and the very weird system state adjustments that then occur will be a revolution once they got the kinks worked out.
Damn, it's just insane the levels of miniaturization being achieved. I remember reading numerous articles a few years ago about the challenges and obstacles in silicon going down to this level. I wonder what they're doing to resolve the problem of physics and keeping those electrons going where they're supposed to go.
Somewhere out there is the next chapter of fabrication processes. Silicon is fast-becoming an obsolete material to use. What's next?
Well, just knowing where they are at that level is a challenge, cause the electrons position is a wave function and part of that electron is beyond the gate... Oh my.
Reducing the voltage and frequency I suppose reduces how much bleeds through but then you got some slow ass chip.
Accepting the bleed and finding a way to detect a less than ideal threshold can work. Also trying to better spread out the contact surface would help.
Didn't they try to wrap the gate (not just in a plane but in 3D) to alleviate this or am I thinking of something else entirely.
The Uncertainty Principle comes into play as well. As the trace shrinks toward atomic size, the electron’s position becomes more pinned down, thus it’s velocity becomes more uncertain, leading to strange quantum effects.
Kinda linked to what I said; the electron's position is probabilistic, you know how much chance it has to be there, but that's doesn't mean its there!
The trace if just the place were its more likely it will be, they're trying to corral a wild horse at that level. It's half way out and in .
Tunneling has to do with the fact that at that level, everything has a particle-wave duality.
Having switches that are not just on or off, but exploits this "dimmer" nature and the very weird system state adjustments that then occur will be a revolution once they got the kinks worked out.
“There was a time when the newspapers said that only twelve men understood the theory of relativity. I do not believe there ever was such a time ... On the other hand, I think I can safely say that nobody understands quantum mechanics.”
Damn, it's just insane the levels of miniaturization being achieved. I remember reading numerous articles a few years ago about the challenges and obstacles in silicon going down to this level. I wonder what they're doing to resolve the problem of physics and keeping those electrons going where they're supposed to go.
Somewhere out there is the next chapter of fabrication processes. Silicon is fast-becoming an obsolete material to use. What's next?
It’s even more sad is, I remember talk of going sub micron would make chips too fragile to hold and work with making manufacture nearly impossible.
Damn, it's just insane the levels of miniaturization being achieved. I remember reading numerous articles a few years ago about the challenges and obstacles in silicon going down to this level. I wonder what they're doing to resolve the problem of physics and keeping those electrons going where they're supposed to go.
Somewhere out there is the next chapter of fabrication processes. Silicon is fast-becoming an obsolete material to use. What's next?
It’s even more sad is, I remember talk of going sub micron would make chips too fragile to hold and work with making manufacture nearly impossible.
Maybe I’m overthinking this, but “scaled back” does not seem like the appropriate term when describing this technical achievement. Yes, I get that it is a smaller process.
Yeah, it’s not the best synonym for “a reduction” (which would be better). Or, you could say “a process shrink,” which would confer some context to “Shrinking” in the next sentence.
In my reading, the phrase seems to have almost a negative connotation, used to imply a down-sizing—or even right-sizing—from some previous, overly-optimistic (or preferred) target: a scaled back IPO, scaled back expansion plans, a scaled back manufacturing ramp, a scaled back software release, scaled back R&D expenditures.
But, I mainly proof/edit business writing, so maybe my exposure is limited. (Not meaning to be too critical Roger!)
3nm is also part of 5nm in TSMC terms. Much like how 20 / 14 nm and 10 / 7nm are played.
So
2017 10nm
2018 7nm
2019 7nm+
2020 5nm*
2021 3nm*
2022 3nm+*
I am guessing the new Fab has something to do with EUV, where TSMC has it planned to be around 2020 / 2021. Since nothing about EUV is confirmed yet ( it is always another year and ASML will make it ), likely TSMC has a few backup plan incase things do get wrong.
Somewhere in the future, we will have to use something other then silicon as we reach the point where smaller nodes brings negligible benefits at cost may be even Apple dont want to go.
What happens when we hit 1 nanometer? Does chip development end there?
Well we could consider measuring in picometers instead. That's assuming that technology is developed to take processes to that level of miniaturisation.
However there's a real problem in that a silicon atom is 210pm across itself. Carbon is a bit smaller. 1nm processes will likely use graphene.
If you want to know how long process technology takes to mature, the first 5nm transistor was made by NEC in 2003, and the first 3nm transistor was made in Korea in 2006. It takes a while to be able to put billions of them together happily on a chip.
7nm A12 may have 5-7 billion transistors, 5nm A14/A15 may have 8-12 billion. 3nm A16/A17/A18 may have 15-20 billion.
An atom exists between zero and one. There was supposed to be inescapable transistor jumping at 5 nanometers, last I read. I realize that it's thanks to the use of new materials that we've even gotten down this far, but there comes a point when your transistors are smaller than the width of an atom and you start running into quantum effects that we can't begin to calculate, much less engineer around.
They already made 1nm functional transistors, 3nm are going to enter MASS PRODUCTION in 4 years.
Well, alleged 3nm enters production... But it is not really 3nm if you use even today's measure (let alone 10 years ago).
Also, the question is not can they produce it, the question is can they produce something at a cost that makes sense and will there be clients at that cost.
By the time 3nm gets in production, it will be 18 years since its been done in the lab. If this happens for 1nm, then the current race to something smaller will mostly grind to a halt. Unless they use some other tech to get better performance; this is always possible though right now there is no obvious successor.
Great to see those discussions! There might be a different dimension though... Those lenghts are EQUIVALENT ones so that we can benchmark with the older materials used. In practice physical lenghts haven't scaled below 20 something nm .... (exact number to be debated). It is the new material and techniques (high k metal gate so that you better control of the channel, low k interconnects, and what not) that give a speed advantage. (Not exact) words of Bram N.
What about integration density then? Does it improve or not (since physical dimensions do not really follow)? Need to research this a bit...
Comments
Maybe I’m overthinking this, but “scaled back” does not seem like the appropriate term when describing this technical achievement. Yes, I get that it is a smaller process.
-Feynman
In my reading, the phrase seems to have almost a negative connotation, used to imply a down-sizing—or even right-sizing—from some previous, overly-optimistic (or preferred) target: a scaled back IPO, scaled back expansion plans, a scaled back manufacturing ramp, a scaled back software release, scaled back R&D expenditures.
But, I mainly proof/edit business writing, so maybe my exposure is limited. (Not meaning to be too critical Roger!)
Well we could consider measuring in picometers instead. That's assuming that technology is developed to take processes to that level of miniaturisation.
However there's a real problem in that a silicon atom is 210pm across itself. Carbon is a bit smaller. 1nm processes will likely use graphene.
If you want to know how long process technology takes to mature, the first 5nm transistor was made by NEC in 2003, and the first 3nm transistor was made in Korea in 2006. It takes a while to be able to put billions of them together happily on a chip.
7nm A12 may have 5-7 billion transistors, 5nm A14/A15 may have 8-12 billion. 3nm A16/A17/A18 may have 15-20 billion.
There might be a different dimension though...
Those lenghts are EQUIVALENT ones so that we can benchmark with the older materials used.
In practice physical lenghts haven't scaled below 20 something nm .... (exact number to be debated).
It is the new material and techniques (high k metal gate so that you better control of the channel, low k interconnects, and what not) that give a speed advantage. (Not exact) words of Bram N.
What about integration density then? Does it improve or not (since physical dimensions do not really follow)?
Need to research this a bit...