Lengthen all the pipelines again to 10 or 14 to ensure higher clock rates
Double the number of register reservation stations
Double the dispatch and completion unit capacity
Add an on-die memory controller or high speed bus interface
Put the largest L2 cache possible on-die
Hmmm. That sounds just like a G5 to me, no matter what you call it or what it was based on originally.</strong>
You know what the G5 architecture is like! Holy mackeral, Programmer. You better make sure the MIBs aren't outside.
Yes, that's why I said it was straight forward. There really isn't that much magic to understanding this stuff. It's all in the number of transistors Motorola wants to spend. Problem is that I really can't think of a good reason for Motorola to design something like that for their own needs. Apple may have enough leverage to get them to do it, but it isn't exactly in Moto's best interest when their market demands a more specialized CPU.
<strong>No single bullet item is that hard, but they add up to quite a bit of work. ... The last round of rumours (7560 & 7500) could actually be this strategy -- take half my list and put it into the 7560, and add the other half in the 7500.</strong>
Well, yes, that's pretty much it.
1) Fab the 7455 on HiP 7 for portables. Perhaps also modify for DDR at same time.
2) Modify the 7455 into a hypothetical 7460/7470 by increasing issue/completion width to 4, add another scalar FPU, new bus design, 4 MB backside L3 cache, all the other little things needed to support the changes (buffers, entries, et al), and fab it on HiP 7.
3) Fab hypothetical 7460/7470 on HiP 8 (a hypothetical 0.09 micron process).
(By this time it would be what, late 2004?)
4) Modify once more for 64 bit IUs, double precision AltiVec, add new cache design, improved bus, and more pipeline stages to form a 7500.
<strong>I'm not a big fan of longer pipes, either, but if its an overall win then it makes sense.</strong>
I don't really care about the technicalities of shallowly or deeply pipeline architectures. I do understand that from a marketing perspective, a deeply pipelined processor has a resonant marketing advantage with each successive process improvement. That is, for each new fab process, a deeply pipeline processor will have increasingly more MHz that a comparitive shallowly pipelined processor on said process. Intel understands this very well, and they are one of the very few companies capable of the investments needed for ever advancing fabrication technology.
Certainly there is a careful balance. Being too shallow or too deep all have their consequences in regard to the competition.
<strong>Certainly more super-scalar is interesting, but even with the 604 they were running into the problem of how to keep all those units busy</strong>
Quad-issue was a little excessive in those days yes. But we're getting to the point that it would be the norm. One of the problems with the 604 perhaps, and it still is today, is that compilers for PPC are abysmal. On top of that, memory architectures on Apple systems are not that good.
However, I do think Apple would have been better off if they decided to take care of their CPU destiny at that time by taking the 604 design and adding the same sort of improvements seen in the succeeding years (backside cache, on-die L2 cache, SIMD, deeper pipeline, etc). The good thing about this is that they could have keep cloning alive and still be profittable by always having the fastest CPU. Assuming they could have out-design Moto and IBM of course. Or perhaps they could have contracted IBM for a 604 based design since it was theirs in the 1st place.
<strong>I don't think we'll see truly huge caches. Off-chip caches are better replaced by a faster memory system (i.e. HyperTransport or RapidIO to fast memory), and there are limits to how big you want to push the L2 cache. ... As a cache's size increases its effect on performance diminishes, so there is a real "sweat spot" that currently seems to be about 0.5 megabytes for the onchip L2. ...</strong>
My supposition on cache sizes is based on what I think the software loads are going to be like in the future, growing a lot, and based on large memory architectures falling behind processor performance as time goes by. Both of which I think you would agree is true.
Memory demands would sort of follow Moore's "Law" and double every 1 to 2 years. So, I don't think it's going to be 128 to 256 MB seen today, but rather in the multi-GByte range in a few years. I see a move away from filesystem style storage to database style storage system and intelligent agents. I think there is going to be a lot of very complex software that needs to run as fast as possible. Sort of like the stresses seen on mainframe, workstation and server processors seen today, but for the consumer.
As far as memory is concerned, I think people are more a victim of MT/sec numbers being transcribed into MHz numbers than the MHz numbers would indicate. Ie, DDR266 memory isn't really twice as fast as PC133 memory. Quad data rate memory (533) isn't really 4 times as PC133. Just only for sequential accesses. So CPU clock rates are going ever higher, while memory is moving at a crawl which would necessitate larger cache designs when the software loads go higher.
Yes, that's why I said it was straight forward. There really isn't that much magic to understanding this stuff. It's all in the number of transistors Motorola wants to spend. Problem is that I really can't think of a good reason for Motorola to design something like that for their own needs. Apple may have enough leverage to get them to do it, but it isn't exactly in Moto's best interest when their market demands a more specialized CPU.</strong><hr></blockquote>
Oh, I don't know. Now that the G4 has attracted Cisco's attention they have another customer who'll buy the fastest chips they can make as fast as they can make them.
[quote]<strong>1) Fab the 7455 on HiP 7 for portables. Perhaps also modify for DDR at same time.
2) Modify the 7455 into a hypothetical 7460/7470 by increasing issue/completion width to 4, add another scalar FPU, new bus design, 4 MB backside L3 cache, all the other little things needed to support the changes (buffers, entries, et al), and fab it on HiP 7.
3) Fab hypothetical 7460/7470 on HiP 8 (a hypothetical 0.09 micron process).
(By this time it would be what, late 2004?)
4) Modify once more for 64 bit IUs, double precision AltiVec, add new cache design, improved bus, and more pipeline stages to form a 7500.</strong><hr></blockquote>
Actually, at the rate Mot's been revising the 745x series I think late 2004 for a HiP8 7470 is pessimistic.
[quote]<strong>However, I do think Apple would have been better off if they decided to take care of their CPU destiny at that time by taking the 604 design and adding the same sort of improvements seen in the succeeding years (backside cache, on-die L2 cache, SIMD, deeper pipeline, etc).</strong><hr></blockquote>
There was in fact a 604ev-derived "G3" processor in the works, with its own high-end motherboard, to replace the Tsunami. The project was killed as too expensive when Apple discovered how well the 603e-derived G3 performed on the consumer Gossamer board. That's how Apple was able to slash the prices on the PowerMacs when they went to the G3.
There was in fact a 604ev-derived "G3" processor in the works, with its own high-end motherboard, to replace the Tsunami. The project was killed as too expensive when Apple discovered how well the 603e-derived G3 performed on the consumer Gossamer board. That's how Apple was able to slash the prices on the PowerMacs when they went to the G3.
I thought what they killed was the project being worked on by Exponential. A stripped down 604 made on a 500nm(!) biPolar (vs CMOS) process. At the time it was supposed to get 533MHz.
[QB3) Fab hypothetical 7460/7470 on HiP 8 (a hypothetical 0.09 micron process).
(By this time it would be what, late 2004?)
[/QB]<hr></blockquote>
Was slated for completion in late 2003 actually. But with AMD pulling out of alliance with Moto I don't know what that has done to their time schedule.
I thought what they killed was the project being worked on by Exponential. A stripped down 604 made on a 500nm(!) biPolar (vs CMOS) process. At the time it was supposed to get 533MHz.</strong><hr></blockquote>
They killed that, too, but this was a different project. Apple had planned to keep the distinction they had where the 603 powered the consumer offerings and the 604 powered the pro offerings before (what became known as) the G3 impressed them enough to standardize on the cheaper architecture.
There was in fact a 604ev-derived "G3" processor in the works, with its own high-end motherboard, to replace the Tsunami. The project was killed as too expensive when Apple discovered how well the 603e-derived G3 performed on the consumer Gossamer board.</strong>
I'm not so sure that is an accurate assessment. I think it was more that the Power Mac G3 (the original) machines outperformed the Power Mac 8600/9600 which were using 604e processors. Which isn't surprising since the Power Mac G3 had a better memory architecture all the way around.
My guess is that there never really was a 604e derived G3 processor, at least a serious attempt at one, for a couple of reasons. The 750 was essentially a junior 604e, minus one simple IU but one huge addition being the backside L2 cache. The backside cache and additional IU (to make 2 to the 604's 3) added to the 603e made up the difference and then some.
If Moto and IBM planned a 3rd generation PPC based on the 604, at the very least, they would have added backside cache which should have giving it enough memory bandwidth to outperform the 750 in both int and fp by about 5 to 10%. Also adding another FP along with the backside cache would have been intriguing, but at that point in time, I don't think Moto and IBM thought the investment would have been worth it, since the 750 got them most of what they wanted.
Since Apple had no 604e derived processor to use for the Power Express machines and that the 750 performed better than the 604e, they were left with using the 750 for the 6 slot machines or killing them.
Btw, in terms of cost, the 604e should have been cheaper than the 750 because it's die size was about 30% less that of the 750 on the same process. So, I wouldn't be so sure the 750 being cheaper than a 604e derived G3 as that true either.
[HiP 9] was slated for completion in late 2003 actually. But with AMD pulling out of alliance with Moto I don't know what that has done to their time schedule.</strong>
Isn't completion (HiP 9) and shipping XXX microprocessor on said process totally unrelated
[quote]Originally posted by Eric D.V.H:<hr></blockquote>
Thanks for the reply. A couple minor points --
[quote]
Copland was practically done(For those whom would refute me. I point to the fact of that. mere months after being fired. the Copland team regrouped, formed Be, made BeOS.
<hr></blockquote>
Did they get fired or did the all resign in mass? Anyway it was kind of funny - Apple was hyping Copeland as RsN at some conference while they were running like 20 MacOS Engineer recs in the SJ Mercury News.
My understanding is that the plan for Copeland was that it would break all drivers and most-to-all programs, while still not providing full PMT and memory protection (that was for "Gershwin"). That sounds more like a management problem than an engineering one.
[quote]
DEC's failure?
<hr></blockquote>
Little story - back in 1994-5 or so I worked at big NT 3.51 shop. We had Pentium-class servers everwhere and desparately needed consolidation. On two seperate occasssions, we had DEC come in to demo their Alpha servers, and on neither occassion could their sales engineers get the things to even boot up. When the 4-way PPros shipped, we started buying them like crazy.
There was a real window there for NT on RISC, but for whatever reason it never caught on. Part of that must had to do with Digital, who was in a huge decline at the time.
[quote]Originally posted by Eric D.V.H:
Who knows. but if you ask me. I think it was all a massively orchestrated plot of darkness, evil and FUD by Intel and possibly Microsoft. to SCARE those involved with RISC into hesitating long enough for Intel to come at their throats. as well as to bring such fear into some of them. that they would come crawling and begging on their knees(Read: HP) to Intel for mercy. but that's just my opinion. also. most of this transpired before the internet really took off(1993-1998).
<hr></blockquote>
Whatever it was, it worked. Sun and Intel cleaned up while those that had stalled their product plans are in serious trouble. HP/Compaq merger seems to be nothing more than raising the whiteflag in the midrange. PowerPC might be a nitch in the desktop space, but it would be nice to see at least a tiny sign of life from IBM/Moto.
Isn't completion (HiP 9) and shipping XXX microprocessor on said process totally unrelated </strong><hr></blockquote>
You misquoted my quote somehow to read HiP9 rather than HiP8 first of all . Last I saw HiP9 was still up in the air for introduction in 2005 with an ongoing debate of whether it would be accomplished with 157nm or EUV lithography. But that's another subject .
It's not a totally unrelated event, a process completed and a microprocessor shipped on said process. Certainly a process is validated on a nice simple repetitive structure like SRAM first and then integrated into more complex devices like MPUs. But the ability to be able to reliably manufacture any device at 90nm (95 perhaps) is an important milestone. Depending on the company, economics, and the priority a microprocessor could be produced within 6-18 months at fairly mature levels.
Using some very rough metrics AMD will have moved their Athlon processor from .18 to .13 approximately 6 months after certification of HiP7. (Rough as in I know when Moto's MOS13 was qualified for HiP7 and I know when AMD is shipping .13 Athlons, so there is a bit of leeway involved )
Comments
So the should really take the G4 and...
- Add another complex integer unit (or two)
- Add another FPU unit (or two)
- Extend the integer registers to 64-bit
- Extend all the integer units to 64-bit
- Lengthen all the pipelines again to 10 or 14 to ensure higher clock rates
- Double the number of register reservation stations
- Double the dispatch and completion unit capacity
- Add an on-die memory controller or high speed bus interface
- Put the largest L2 cache possible on-die
Hmmm. That sounds just like a G5 to me, no matter what you call it or what it was based on originally.</strong>You know what the G5 architecture is like! Holy mackeral, Programmer. You better make sure the MIBs aren't outside.
Yes, that's why I said it was straight forward. There really isn't that much magic to understanding this stuff. It's all in the number of transistors Motorola wants to spend. Problem is that I really can't think of a good reason for Motorola to design something like that for their own needs. Apple may have enough leverage to get them to do it, but it isn't exactly in Moto's best interest when their market demands a more specialized CPU.
<strong>No single bullet item is that hard, but they add up to quite a bit of work. ... The last round of rumours (7560 & 7500) could actually be this strategy -- take half my list and put it into the 7560, and add the other half in the 7500.</strong>
Well, yes, that's pretty much it.
1) Fab the 7455 on HiP 7 for portables. Perhaps also modify for DDR at same time.
2) Modify the 7455 into a hypothetical 7460/7470 by increasing issue/completion width to 4, add another scalar FPU, new bus design, 4 MB backside L3 cache, all the other little things needed to support the changes (buffers, entries, et al), and fab it on HiP 7.
3) Fab hypothetical 7460/7470 on HiP 8 (a hypothetical 0.09 micron process).
(By this time it would be what, late 2004?)
4) Modify once more for 64 bit IUs, double precision AltiVec, add new cache design, improved bus, and more pipeline stages to form a 7500.
<strong>I'm not a big fan of longer pipes, either, but if its an overall win then it makes sense.</strong>
I don't really care about the technicalities of shallowly or deeply pipeline architectures. I do understand that from a marketing perspective, a deeply pipelined processor has a resonant marketing advantage with each successive process improvement. That is, for each new fab process, a deeply pipeline processor will have increasingly more MHz that a comparitive shallowly pipelined processor on said process. Intel understands this very well, and they are one of the very few companies capable of the investments needed for ever advancing fabrication technology.
Certainly there is a careful balance. Being too shallow or too deep all have their consequences in regard to the competition.
<strong>Certainly more super-scalar is interesting, but even with the 604 they were running into the problem of how to keep all those units busy</strong>
Quad-issue was a little excessive in those days yes. But we're getting to the point that it would be the norm. One of the problems with the 604 perhaps, and it still is today, is that compilers for PPC are abysmal. On top of that, memory architectures on Apple systems are not that good.
However, I do think Apple would have been better off if they decided to take care of their CPU destiny at that time by taking the 604 design and adding the same sort of improvements seen in the succeeding years (backside cache, on-die L2 cache, SIMD, deeper pipeline, etc). The good thing about this is that they could have keep cloning alive and still be profittable by always having the fastest CPU. Assuming they could have out-design Moto and IBM of course. Or perhaps they could have contracted IBM for a 604 based design since it was theirs in the 1st place.
<strong>I don't think we'll see truly huge caches. Off-chip caches are better replaced by a faster memory system (i.e. HyperTransport or RapidIO to fast memory), and there are limits to how big you want to push the L2 cache. ... As a cache's size increases its effect on performance diminishes, so there is a real "sweat spot" that currently seems to be about 0.5 megabytes for the onchip L2. ...</strong>
My supposition on cache sizes is based on what I think the software loads are going to be like in the future, growing a lot, and based on large memory architectures falling behind processor performance as time goes by. Both of which I think you would agree is true.
Memory demands would sort of follow Moore's "Law" and double every 1 to 2 years. So, I don't think it's going to be 128 to 256 MB seen today, but rather in the multi-GByte range in a few years. I see a move away from filesystem style storage to database style storage system and intelligent agents. I think there is going to be a lot of very complex software that needs to run as fast as possible. Sort of like the stresses seen on mainframe, workstation and server processors seen today, but for the consumer.
As far as memory is concerned, I think people are more a victim of MT/sec numbers being transcribed into MHz numbers than the MHz numbers would indicate. Ie, DDR266 memory isn't really twice as fast as PC133 memory. Quad data rate memory (533) isn't really 4 times as PC133. Just only for sequential accesses. So CPU clock rates are going ever higher, while memory is moving at a crawl which would necessitate larger cache designs when the software loads go higher.
<strong>
Yes, that's why I said it was straight forward. There really isn't that much magic to understanding this stuff. It's all in the number of transistors Motorola wants to spend. Problem is that I really can't think of a good reason for Motorola to design something like that for their own needs. Apple may have enough leverage to get them to do it, but it isn't exactly in Moto's best interest when their market demands a more specialized CPU.</strong><hr></blockquote>
Oh, I don't know. Now that the G4 has attracted Cisco's attention they have another customer who'll buy the fastest chips they can make as fast as they can make them.
[quote]<strong>1) Fab the 7455 on HiP 7 for portables. Perhaps also modify for DDR at same time.
2) Modify the 7455 into a hypothetical 7460/7470 by increasing issue/completion width to 4, add another scalar FPU, new bus design, 4 MB backside L3 cache, all the other little things needed to support the changes (buffers, entries, et al), and fab it on HiP 7.
3) Fab hypothetical 7460/7470 on HiP 8 (a hypothetical 0.09 micron process).
(By this time it would be what, late 2004?)
4) Modify once more for 64 bit IUs, double precision AltiVec, add new cache design, improved bus, and more pipeline stages to form a 7500.</strong><hr></blockquote>
Actually, at the rate Mot's been revising the 745x series I think late 2004 for a HiP8 7470 is pessimistic.
[quote]<strong>However, I do think Apple would have been better off if they decided to take care of their CPU destiny at that time by taking the 604 design and adding the same sort of improvements seen in the succeeding years (backside cache, on-die L2 cache, SIMD, deeper pipeline, etc).</strong><hr></blockquote>
There was in fact a 604ev-derived "G3" processor in the works, with its own high-end motherboard, to replace the Tsunami. The project was killed as too expensive when Apple discovered how well the 603e-derived G3 performed on the consumer Gossamer board. That's how Apple was able to slash the prices on the PowerMacs when they went to the G3.
[ 03-15-2002: Message edited by: Amorph ]</p>
I thought what they killed was the project being worked on by Exponential. A stripped down 604 made on a 500nm(!) biPolar (vs CMOS) process. At the time it was supposed to get 533MHz.
A 620 derived G3 or G4 chip would have ruled.
G-News
[QB3) Fab hypothetical 7460/7470 on HiP 8 (a hypothetical 0.09 micron process).
(By this time it would be what, late 2004?)
[/QB]<hr></blockquote>
Was slated for completion in late 2003 actually. But with AMD pulling out of alliance with Moto I don't know what that has done to their time schedule.
<strong>
I thought what they killed was the project being worked on by Exponential. A stripped down 604 made on a 500nm(!) biPolar (vs CMOS) process. At the time it was supposed to get 533MHz.</strong><hr></blockquote>
They killed that, too, but this was a different project. Apple had planned to keep the distinction they had where the 603 powered the consumer offerings and the 604 powered the pro offerings before (what became known as) the G3 impressed them enough to standardize on the cheaper architecture.
[ 03-15-2002: Message edited by: Amorph ]</p>
There was in fact a 604ev-derived "G3" processor in the works, with its own high-end motherboard, to replace the Tsunami. The project was killed as too expensive when Apple discovered how well the 603e-derived G3 performed on the consumer Gossamer board.</strong>
I'm not so sure that is an accurate assessment. I think it was more that the Power Mac G3 (the original) machines outperformed the Power Mac 8600/9600 which were using 604e processors. Which isn't surprising since the Power Mac G3 had a better memory architecture all the way around.
My guess is that there never really was a 604e derived G3 processor, at least a serious attempt at one, for a couple of reasons. The 750 was essentially a junior 604e, minus one simple IU but one huge addition being the backside L2 cache. The backside cache and additional IU (to make 2 to the 604's 3) added to the 603e made up the difference and then some.
If Moto and IBM planned a 3rd generation PPC based on the 604, at the very least, they would have added backside cache which should have giving it enough memory bandwidth to outperform the 750 in both int and fp by about 5 to 10%. Also adding another FP along with the backside cache would have been intriguing, but at that point in time, I don't think Moto and IBM thought the investment would have been worth it, since the 750 got them most of what they wanted.
Since Apple had no 604e derived processor to use for the Power Express machines and that the 750 performed better than the 604e, they were left with using the 750 for the 6 slot machines or killing them.
Btw, in terms of cost, the 604e should have been cheaper than the 750 because it's die size was about 30% less that of the 750 on the same process. So, I wouldn't be so sure the 750 being cheaper than a 604e derived G3 as that true either.
[HiP 9] was slated for completion in late 2003 actually. But with AMD pulling out of alliance with Moto I don't know what that has done to their time schedule.</strong>
Isn't completion (HiP 9) and shipping XXX microprocessor on said process totally unrelated
Thanks for the reply. A couple minor points --
[quote]
Copland was practically done(For those whom would refute me. I point to the fact of that. mere months after being fired. the Copland team regrouped, formed Be, made BeOS.
<hr></blockquote>
Did they get fired or did the all resign in mass? Anyway it was kind of funny - Apple was hyping Copeland as RsN at some conference while they were running like 20 MacOS Engineer recs in the SJ Mercury News.
My understanding is that the plan for Copeland was that it would break all drivers and most-to-all programs, while still not providing full PMT and memory protection (that was for "Gershwin"). That sounds more like a management problem than an engineering one.
[quote]
DEC's failure?
<hr></blockquote>
Little story - back in 1994-5 or so I worked at big NT 3.51 shop. We had Pentium-class servers everwhere and desparately needed consolidation. On two seperate occasssions, we had DEC come in to demo their Alpha servers, and on neither occassion could their sales engineers get the things to even boot up. When the 4-way PPros shipped, we started buying them like crazy.
There was a real window there for NT on RISC, but for whatever reason it never caught on. Part of that must had to do with Digital, who was in a huge decline at the time.
[quote]Originally posted by Eric D.V.H:
Who knows. but if you ask me. I think it was all a massively orchestrated plot of darkness, evil and FUD by Intel and possibly Microsoft. to SCARE those involved with RISC into hesitating long enough for Intel to come at their throats. as well as to bring such fear into some of them. that they would come crawling and begging on their knees(Read: HP) to Intel for mercy. but that's just my opinion. also. most of this transpired before the internet really took off(1993-1998).
<hr></blockquote>
Whatever it was, it worked. Sun and Intel cleaned up while those that had stalled their product plans are in serious trouble. HP/Compaq merger seems to be nothing more than raising the whiteflag in the midrange. PowerPC might be a nitch in the desktop space, but it would be nice to see at least a tiny sign of life from IBM/Moto.
<strong>
Isn't completion (HiP 9) and shipping XXX microprocessor on said process totally unrelated
You misquoted my quote somehow to read HiP9 rather than HiP8 first of all
It's not a totally unrelated event, a process completed and a microprocessor shipped on said process. Certainly a process is validated on a nice simple repetitive structure like SRAM first and then integrated into more complex devices like MPUs. But the ability to be able to reliably manufacture any device at 90nm (95 perhaps) is an important milestone. Depending on the company, economics, and the priority a microprocessor could be produced within 6-18 months at fairly mature levels.
Using some very rough metrics AMD will have moved their Athlon processor from .18 to .13 approximately 6 months after certification of HiP7. (Rough as in I know when Moto's MOS13 was qualified for HiP7 and I know when AMD is shipping .13 Athlons, so there is a bit of leeway involved