remember double the TSMC process size to get the “real” size compared to intel... (IMO the process size should be the metal interconnect pitch... but then that would not be “exciting”, “new”, “amazing”... and it would not describe the minimum distance between two “silicon” lines.)
BTW, IMO anything at 5TSMC or 10intel will long time coming... and IMO anything smaller than that... wishful thinking.
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BTW, IMO anything at 5TSMC or 10intel will long time coming... and IMO anything smaller than that... wishful thinking.