I don't think bus throughput will be that much faster for single processor systems, but since the bus on the 970 doesn't have to be shared, in DP systems, throughput will be more like 10 times higher than the G4, if Apple/IBM creates a companion chip to support it. Memory-tech, unluckily, doesn't keep up.
I don't think bus throughput will be that much faster for single processor systems
Oh yes it will, and it'll show up in code that reads and writes extensively to memory (including dumb ported Windows code that isn't aware that it has zillions of registers to play with), and the bandwidth-starved AltiVec unit, which on a G4 is capable of devouring roughly 12 times the amount of data that MaxBus can feed it. The approximately five-fold bandwidth increase offered by the GigaBus still won't be enough, but it'll be a huge improvement for any AltiVec code that isn't overwhelmingly processor bound.
In dual processor systems, unless Apple uses the GigaBus linked ring topology that Programmer is wondering about, the available bandwidth will be even more plentiful, but this advantage will be largely theoretical unless Apple ships SMP systems with faster RAM than single-CPU systems.
What I meant is that throughput will not be 6-7 times better (what was what "that" referred to), more like 5, and yes, it will show up and be very significant to memory-intensive code! I agree with you, Amorph
The speculation Programmer is talking about is for multiprocessor topologies. I think Apple will only go dual at most and will just use a system/memory controller that supports 2 PPC 970s directly. Anything more would involve a switched fabric. A ring topology would have some weird latency issues, and we don't even know if it would even physically support such a configuration.
I should be clear that personally I don't think the 970 will use a ring topology bus, I was just repeating an interesting speculation raised on Ars that offered a possibility that had never even occured to me. And whether Apple would use such a topology would depend on whether that was the IBM-defined and implemented bus design in the 970, not the other way around. Apple has to live with what IBM provides.
I should be clear that personally I don't think the 970 will use a ring topology bus, I was just repeating an interesting speculation raised on Ars that offered a possibility that had never even occured to me. And whether Apple would use such a topology would depend on whether that was the IBM-defined and implemented bus design in the 970, not the other way around. Apple has to live with what IBM provides.
So do I think.
The ring topology doesn't make real sense to me, in 4 and 8-way systems IBM intends the 970 for. Since the 970 is capable of executing such huge loads of instructions, it also needs similiarly huge loads of bandwidth to shuffle instructions and data to and from the processor. In a 4/8-way system with a ring topoogy, you're sitting with 3.2GB/s of bandwidth for all the processors in total, which is less than each G4 in SP systems have now, plus some weird latency issues. If the data is sent through 4/8 processors (?) in total, I assume there will be created much higher bandwidth, and an unneccesary overhead for "disturbing" the inappropriate processors/devices the data is sent through. If this is correct, I don't see any reason for IBM to provide the 970 with so many execution-units, if they're going to just stay idle alot of the time.
I'm not knowing what I talk about now, it's just a thought
When IBM have invested so much in creating a really capable and wide execution core, and equipped the processor with this really data-hungry SIMD-unit, I must admit I think it sounds pretty stupid to waste it by crippling it with a slow supply of data and instructions. This sounds amazingly similiar to another well-known situation
Programmer: Are you saying that we're going to have to end up with one of the topologies, either ring- or star-based? I were hoping that Apple would be able to choose between the two...
I should be clear that personally I don't think the 970 will use a ring topology bus, I was just repeating an interesting speculation raised on Ars that offered a possibility that had never even occured to me.
You mean like this:
Code:
--------- ---------
--------| PPC |<---------| PPC |<--------
| ----->| 970 |--------->| 970 |------- |
| | --------- --------- | |
| | | |
| | ------------ | |
| ---------------| System |<--------------- |
---------------->| ASIC |------------------
| |
AGP --------| |-------- RAM
| |
PCI --------| |-------- AGP
| |
ATA --------| |-------- Ethernet
| |
------------
|
|
southbridge
It makes things very simple, especially a multiprocessor daughtercard and its socket. But the MPF presentation said the 970 bus is point-to-point and source synchronous. If I understand point-to-point and source synchronous correctly, there can only be 2 things on the bus, a driver and a receiver, which means the receiver has to be a core logic ASIC.
Ring topologies are natural fits for chips with on-chip memory controllors, like the Opteron or the Power4. The Power4 MCM is in fact a superspeed ring network. So maybe, that's where the speculation comes from. But I think IBM intends the 970 to be in mostly uniprocessor and maybe dual processor machines. There is a tremendous simplification between the Power4 and the 970, and all the mechanisms to support large SMP configs where removed.
But I think IBM intends the 970 to be in mostly uniprocessor and maybe dual processor machines. There is a tremendous simplification between the Power4 and the 970, and all the mechanisms to support large SMP configs where removed.
[edit: too many things to mention...]
You may be right, however, the initial IBM press release specifically stated," The design also supports symmetric multi-processing (SMP), allowing systems to be created that link multiple processors to work in tandem for additional processing power."
You may be right, however, the initial IBM press release specifically stated," The design also supports symmetric multi-processing (SMP), allowing systems to be created that link multiple processors to work in tandem for additional processing power."
You're agreeing, seemingly, as you both say, the processor supports SMP and is intended for use in such systems.
Other articles, and (possibly) documents that I'm to lazy to provide linkage too, are suggesting that IBM also intends to use this processor in 4- and 8-way LinuxPPC desktop systems.
Other articles, and (possibly) documents that I'm to lazy to provide linkage too, are suggesting that IBM also intends to use this processor in 4- and 8-way LinuxPPC desktop systems.
I don't believe that at all. The 970 is not intended for 4- or 8-way systems; that's Power4 territory. And 4-way desktop machines are just not economically viable; doubly so with the 970's point-to-point interconnect.
I don't believe that at all. The 970 is not intended for 4- or 8-way systems; that's Power4 territory. And 4-way desktop machines are just not economically viable; doubly so with the 970's point-to-point interconnect.
The 970 is definitely headed for 4- and 8-way systems.
These are IBM systems btw not Apple and they aren't exactly classed as desktop systems like most people here think of desktop systems.
I don't believe that at all. The 970 is not intended for 4- or 8-way systems; that's Power4 territory. And 4-way desktop machines are just not economically viable; doubly so with the 970's point-to-point interconnect.
Tomb's diagram is right -- data travels one way around the ring. Each link on the bus is a point-to-point synchronous link. The question is how they are arranged.
IMO Apple will not be able to choose their topology. It is my belief that the protocol will either be designed for a ring or a star topology, and that protocol is frozen in hardware. Its possible that IBM could implement two protocols, but I think that very unlikely. The two protocols are quite different -- consider that a ring must send all data it receives, and it may receive data it didn't ask for. A star, on the other hand, only gets data it asked for but gets snooping information based on activity of other processors, plus it doesn't have to forward its data to anybody else.
Tomb's diagram is right -- data travels one way around the ring. Each link on the bus is a point-to-point synchronous link. The question is how they are arranged.
Yes, I think so too. But I really have a hard time believing the illustrated ring topology would be implemented.
Quote:
IMO Apple will not be able to choose their topology.
Yes, that has always been the case. Well, for large 4+ processor SMP, they'll probably have a choice.
Quote:
consider that a ring must send all data it receives, and it may receive data it didn't ask for.
Just consider the latency for said unidirectional ring topology. It's crazy.
Just consider the latency for said unidirectional ring topology. It's crazy. [/B]
Yup. Personally, I think the star topology is much more likely but I think that will limit most of Apple's systems to dual configs. You won't see 4 way or 8 way systems (from Apple) unless and until it's feasible to move the memory controller to a switched fabric of some sort.
Comments
Originally posted by r-0X#Zapchud
I don't think bus throughput will be that much faster for single processor systems
Oh yes it will, and it'll show up in code that reads and writes extensively to memory (including dumb ported Windows code that isn't aware that it has zillions of registers to play with), and the bandwidth-starved AltiVec unit, which on a G4 is capable of devouring roughly 12 times the amount of data that MaxBus can feed it. The approximately five-fold bandwidth increase offered by the GigaBus still won't be enough, but it'll be a huge improvement for any AltiVec code that isn't overwhelmingly processor bound.
In dual processor systems, unless Apple uses the GigaBus linked ring topology that Programmer is wondering about, the available bandwidth will be even more plentiful, but this advantage will be largely theoretical unless Apple ships SMP systems with faster RAM than single-CPU systems.
Originally posted by Amorph
Oh yes it will
What I meant is that throughput will not be 6-7 times better (what was what "that" referred to), more like 5, and yes, it will show up and be very significant to memory-intensive code! I agree with you, Amorph
The speculation Programmer is talking about is for multiprocessor topologies. I think Apple will only go dual at most and will just use a system/memory controller that supports 2 PPC 970s directly. Anything more would involve a switched fabric. A ring topology would have some weird latency issues, and we don't even know if it would even physically support such a configuration.
I should be clear that personally I don't think the 970 will use a ring topology bus, I was just repeating an interesting speculation raised on Ars that offered a possibility that had never even occured to me. And whether Apple would use such a topology would depend on whether that was the IBM-defined and implemented bus design in the 970, not the other way around. Apple has to live with what IBM provides.
Originally posted by Programmer
I should be clear that personally I don't think the 970 will use a ring topology bus, I was just repeating an interesting speculation raised on Ars that offered a possibility that had never even occured to me. And whether Apple would use such a topology would depend on whether that was the IBM-defined and implemented bus design in the 970, not the other way around. Apple has to live with what IBM provides.
So do I think.
The ring topology doesn't make real sense to me, in 4 and 8-way systems IBM intends the 970 for. Since the 970 is capable of executing such huge loads of instructions, it also needs similiarly huge loads of bandwidth to shuffle instructions and data to and from the processor. In a 4/8-way system with a ring topoogy, you're sitting with 3.2GB/s of bandwidth for all the processors in total, which is less than each G4 in SP systems have now, plus some weird latency issues. If the data is sent through 4/8 processors (?) in total, I assume there will be created much higher bandwidth, and an unneccesary overhead for "disturbing" the inappropriate processors/devices the data is sent through. If this is correct, I don't see any reason for IBM to provide the 970 with so many execution-units, if they're going to just stay idle alot of the time.
I'm not knowing what I talk about now, it's just a thought
When IBM have invested so much in creating a really capable and wide execution core, and equipped the processor with this really data-hungry SIMD-unit, I must admit I think it sounds pretty stupid to waste it by crippling it with a slow supply of data and instructions. This sounds amazingly similiar to another well-known situation
Programmer: Are you saying that we're going to have to end up with one of the topologies, either ring- or star-based? I were hoping that Apple would be able to choose between the two...
Originally posted by Programmer
I should be clear that personally I don't think the 970 will use a ring topology bus, I was just repeating an interesting speculation raised on Ars that offered a possibility that had never even occured to me.
You mean like this:
--------- ---------
--------| PPC |<---------| PPC |<--------
| ----->| 970 |--------->| 970 |------- |
| | --------- --------- | |
| | | |
| | ------------ | |
| ---------------| System |<--------------- |
---------------->| ASIC |------------------
| |
AGP --------| |-------- RAM
| |
PCI --------| |-------- AGP
| |
ATA --------| |-------- Ethernet
| |
------------
|
|
southbridge
It makes things very simple, especially a multiprocessor daughtercard and its socket. But the MPF presentation said the 970 bus is point-to-point and source synchronous. If I understand point-to-point and source synchronous correctly, there can only be 2 things on the bus, a driver and a receiver, which means the receiver has to be a core logic ASIC.
Ring topologies are natural fits for chips with on-chip memory controllors, like the Opteron or the Power4. The Power4 MCM is in fact a superspeed ring network. So maybe, that's where the speculation comes from. But I think IBM intends the 970 to be in mostly uniprocessor and maybe dual processor machines. There is a tremendous simplification between the Power4 and the 970, and all the mechanisms to support large SMP configs where removed.
[edit: too many things to mention...]
Originally posted by THT
But I think IBM intends the 970 to be in mostly uniprocessor and maybe dual processor machines. There is a tremendous simplification between the Power4 and the 970, and all the mechanisms to support large SMP configs where removed.
[edit: too many things to mention...]
You may be right, however, the initial IBM press release specifically stated," The design also supports symmetric multi-processing (SMP), allowing systems to be created that link multiple processors to work in tandem for additional processing power."
IBM Press Release
IBM unveils 64-bit PowerPC microprocessor
Originally posted by rickag
You may be right, however, the initial IBM press release specifically stated," The design also supports symmetric multi-processing (SMP), allowing systems to be created that link multiple processors to work in tandem for additional processing power."
IBM Press Release
IBM unveils 64-bit PowerPC microprocessor
You're agreeing, seemingly, as you both say, the processor supports SMP and is intended for use in such systems.
Other articles, and (possibly) documents that I'm to lazy to provide linkage too, are suggesting that IBM also intends to use this processor in 4- and 8-way LinuxPPC desktop systems.
Originally posted by r-0X#Zapchud
Other articles, and (possibly) documents that I'm to lazy to provide linkage too, are suggesting that IBM also intends to use this processor in 4- and 8-way LinuxPPC desktop systems.
I don't believe that at all. The 970 is not intended for 4- or 8-way systems; that's Power4 territory. And 4-way desktop machines are just not economically viable; doubly so with the 970's point-to-point interconnect.
Originally posted by wmf
I don't believe that at all. The 970 is not intended for 4- or 8-way systems; that's Power4 territory. And 4-way desktop machines are just not economically viable; doubly so with the 970's point-to-point interconnect.
The 970 is definitely headed for 4- and 8-way systems.
These are IBM systems btw not Apple and they aren't exactly classed as desktop systems like most people here think of desktop systems.
Originally posted by wmf
I don't believe that at all. The 970 is not intended for 4- or 8-way systems; that's Power4 territory. And 4-way desktop machines are just not economically viable; doubly so with the 970's point-to-point interconnect.
http://www.wired.com/news/mac/0,2125,55722,00.html
"This design is aimed at four-way (systems)," said Sampson. "It can certainly support eight-way. It's intended for SMP."
I pretty "Pete Sampson" is just a typo, Peter Sandon is the man.
Originally posted by THT
You mean like this:
Code:
--------- ---------
--------| PPC |<---------| PPC |<--------
| ----->| 970 |--------->| 970 |------- |
| | --------- --------- | |
| | | |
| | ------------ | |
| ---------------| System |<--------------- |
---------------->| ASIC |------------------
| |
AGP --------| |-------- RAM
| |
PCI --------| |-------- AGP
| |
ATA --------| |-------- Ethernet
| |
------------
|
|
southbridge
No more like this:
Thing 1
________________
| |
| |
| |
| |
| | Memory Cntlr
| in out | _______________
---------------- | |
| |__________| in |
| | |
| __________| out |
__|_________|__ | |
| | | |
| out in | ---------------
| |
| |
| |
| |
---------------
Thing 2
IMO Apple will not be able to choose their topology. It is my belief that the protocol will either be designed for a ring or a star topology, and that protocol is frozen in hardware. Its possible that IBM could implement two protocols, but I think that very unlikely. The two protocols are quite different -- consider that a ring must send all data it receives, and it may receive data it didn't ask for. A star, on the other hand, only gets data it asked for but gets snooping information based on activity of other processors, plus it doesn't have to forward its data to anybody else.
Originally posted by Programmer
Tomb's diagram is right -- data travels one way around the ring. Each link on the bus is a point-to-point synchronous link. The question is how they are arranged.
Yes, I think so too. But I really have a hard time believing the illustrated ring topology would be implemented.
IMO Apple will not be able to choose their topology.
Yes, that has always been the case. Well, for large 4+ processor SMP, they'll probably have a choice.
consider that a ring must send all data it receives, and it may receive data it didn't ask for.
Just consider the latency for said unidirectional ring topology.
Originally posted by THT
Just consider the latency for said unidirectional ring topology.
Yup. Personally, I think the star topology is much more likely but I think that will limit most of Apple's systems to dual configs. You won't see 4 way or 8 way systems (from Apple) unless and until it's feasible to move the memory controller to a switched fabric of some sort.