When you say 'G4,' you mean 'the current G4,' right? The 7441s, 7451s, and 7455s that are currently being used are limited to a 133 Mhz bus, but there is no inherent limitation in the architecture, is there?</strong>
There are not any processor buses, at least on the consumer side, that currently operate at clock rates above 133 MHz. Athlons don't. PIVs don't. All of today's buses are parallel buses consisting of 100+ signal lines. To clock all those lines above 133+ MHz synchronously requires some expensive manufacturing. The processor can support higher bus clock rates, but getting it to work on the logic board is a different matter. That's why companies simply can't clock processor buses to 200 MHz or 266 MHz (until manufacturing tech catches up).
To get more bandwidth, what companies have done is change how the signaling is interpreted. Previously, a chip interprets one full sinusoidal wave as a 1 or 0. (A sinusoidal wave is something looks like the tilde (~) on your keyboard.) With a 64 bit bus, that's 64 data lines with 64 sinusoidal waves making up 64 bits of information each clock cycle.
By designing the chips to interpret the rising edge and falling edge of the signal as two bits of data (1 bit for the rising edge and 1 bit for the falling edge), twice as much data can be transferred at the same clock rate. This is what DDR, double data rate, means. 266 MHz, DDR266, PC2100 are all marketing descriptions. In reality, it's really just a 64 bit bus (and memory) that clocks at 133 MHz and is able to transfer 2x64 bits of data per clock cycle.
The G4, any version, does not understand DDR signaling for its processor bus. It's as simple as that, and Moto is the only company that can change it. Literally clocking the bus to 266 MHz or moving to a 128 bit bus (also Moto dependent) are both very expensive options, and Apple really can't go that route.
(RapidIO are HyperTransport are serial buses with far fewer signal lines than parallel buses, and can be clocked much higher.)
<strong>Theoretically, they could release a 7460 (or whatever - maybe a 7500?) that would be completely compatible with current chips, but could use a faster bus, right?</strong>
They could. Motorola already does this for the backside cache bus. The 7455 can support DDR SRAM or regular SRAM for its backside L3 cache.
<strong>Why would they build a bus speed limitation into the chip, as opposed to making it as upward-compatible as possible? Seems backwards that the chip would be bus-dependant and not the other way around....</strong><hr></blockquote>
Not at all, engineering is always about these sorts of limitations and trade-offs. We can only hope that the state-of-affairs at the G4 development lab has advanced sufficiently that DDR capable G4s will soon be shipping.
This question will really expose my utter lack of knowledge of chip design.
I appreciate the information you supplied concerning sinusoidal wave forms and I've always wondered how the chip distinguishes a 0 from a 1.
I would assume the distance between the peaks is constant?? hence the frequency of the chip is set at say 933MHz. Therefore, is it the amplitude or the shape of the peaks and troughs that determine the value to be 0 or 1?
Nah, don't freeze Maya for Windows development. Just make sure that the Mac version always has a few extra "killer" features, and that the windows version is available a good 6 months after the Mac version, and also, make sure that the Windows version hoses the XP system after a few months of up time.
I guarantee it.<hr></blockquote>Well, NAB is here, the G5 is not
Looks like Apple simply has a demo booth and a classroom, not even a session or keynote. <a href="http://www.apple.com/creative/events/nab2002/"; target="_blank">Apple at NAB</a> <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
Saturday...02/23/02... 8pm....the day/time I shook Victor wootens hand for the first(and hopefully not last) time
*such a nerd I am*
</strong><hr></blockquote>
Wow! Have you washed your hand since? How do you play bass with only one hand? Or did you rub your hand on it right afterwards? Did you playing improve?
<strong>Nah, don't freeze Maya for Windows development. Just make sure that the Mac version always has a few extra "killer" features, and that the windows version is available a good 6 months after the Mac version, and also, make sure that the Windows version hoses the XP system after a few months of up time.
He he he...</strong><hr></blockquote>
You know, when people still used WordPerfect, It was rumored that the release of Windows 3.x wasn't ready untill it no longer played nice with M$'s competition.
Comments
When you say 'G4,' you mean 'the current G4,' right? The 7441s, 7451s, and 7455s that are currently being used are limited to a 133 Mhz bus, but there is no inherent limitation in the architecture, is there?</strong>
There are not any processor buses, at least on the consumer side, that currently operate at clock rates above 133 MHz. Athlons don't. PIVs don't. All of today's buses are parallel buses consisting of 100+ signal lines. To clock all those lines above 133+ MHz synchronously requires some expensive manufacturing. The processor can support higher bus clock rates, but getting it to work on the logic board is a different matter. That's why companies simply can't clock processor buses to 200 MHz or 266 MHz (until manufacturing tech catches up).
To get more bandwidth, what companies have done is change how the signaling is interpreted. Previously, a chip interprets one full sinusoidal wave as a 1 or 0. (A sinusoidal wave is something looks like the tilde (~) on your keyboard.) With a 64 bit bus, that's 64 data lines with 64 sinusoidal waves making up 64 bits of information each clock cycle.
By designing the chips to interpret the rising edge and falling edge of the signal as two bits of data (1 bit for the rising edge and 1 bit for the falling edge), twice as much data can be transferred at the same clock rate. This is what DDR, double data rate, means. 266 MHz, DDR266, PC2100 are all marketing descriptions. In reality, it's really just a 64 bit bus (and memory) that clocks at 133 MHz and is able to transfer 2x64 bits of data per clock cycle.
The G4, any version, does not understand DDR signaling for its processor bus. It's as simple as that, and Moto is the only company that can change it. Literally clocking the bus to 266 MHz or moving to a 128 bit bus (also Moto dependent) are both very expensive options, and Apple really can't go that route.
(RapidIO are HyperTransport are serial buses with far fewer signal lines than parallel buses, and can be clocked much higher.)
<strong>Theoretically, they could release a 7460 (or whatever - maybe a 7500?) that would be completely compatible with current chips, but could use a faster bus, right?</strong>
They could. Motorola already does this for the backside cache bus. The 7455 can support DDR SRAM or regular SRAM for its backside L3 cache.
<strong>Why would they build a bus speed limitation into the chip, as opposed to making it as upward-compatible as possible? Seems backwards that the chip would be bus-dependant and not the other way around....</strong><hr></blockquote>
Not at all, engineering is always about these sorts of limitations and trade-offs. We can only hope that the state-of-affairs at the G4 development lab has advanced sufficiently that DDR capable G4s will soon be shipping.
THT
This question will really expose my utter lack of knowledge of chip design.
I appreciate the information you supplied concerning sinusoidal wave forms and I've always wondered how the chip distinguishes a 0 from a 1.
I would assume the distance between the peaks is constant?? hence the frequency of the chip is set at say 933MHz. Therefore, is it the amplitude or the shape of the peaks and troughs that determine the value to be 0 or 1?
1. The same 133MHz bus, and either a higher clocked 7455 (perhaps with even larger L3 caches on die) or a new G4 (process shrunk, etc.).
2. A 133MHz bus that supports DDR and therefore also a new G4 that has been designed to support it (this seems unlikely given your description).
3. An entirely new, RIO-based bus, with an entirely new chip architecture (because presumably existing G4 architectures wouldn't support RIO either).
[ 03-31-2002: Message edited by: Moogs ? ]</p>
'Nab' is a 'multimedia conversion' party conventon for the big boys.
I came across it in a link from Mac Obsever or somewhere...
I'd like Apple to announce that they've just bought Maya out and plan to run it on dual 7500s.
Oh...and that the PC version of Maya has it's development frozen.
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
Lemon Bon Bon
He he he...
So, if I read your description correctly, it is the amplitude(voltage) that results in a 0 or 1.
I guarantee it.<hr></blockquote>Well, NAB is here, the G5 is not
Looks like Apple simply has a demo booth and a classroom, not even a session or keynote. <a href="http://www.apple.com/creative/events/nab2002/"; target="_blank">Apple at NAB</a> <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
<strong>
We're going to get what we want and we'll get it by mid-summer, so cheeeeel.
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" /> </strong><hr></blockquote>
Couldn't have said it better myself. ..bravo!
<strong>
Saturday...02/23/02... 8pm....the day/time I shook Victor wootens hand for the first(and hopefully not last) time
*such a nerd I am*
Wow! Have you washed your hand since? How do you play bass with only one hand? Or did you rub your hand on it right afterwards? Did you playing improve?
<strong>Nah, don't freeze Maya for Windows development. Just make sure that the Mac version always has a few extra "killer" features, and that the windows version is available a good 6 months after the Mac version, and also, make sure that the Windows version hoses the XP system after a few months of up time.
He he he...</strong><hr></blockquote>
You know, when people still used WordPerfect, It was rumored that the release of Windows 3.x wasn't ready untill it no longer played nice with M$'s competition.