Ok, so the writer gets it wrong, as so many others have when it comes to the M series RAM packaging. One would think that’s this simple thing would be well understood by now. So let me make it very clear - the RAM is NOT on the chip. It is NOT “in the CPU itself”. As we should all know by now, it’s in two packages soldered to the substrate, which is the small board the the SoC is itself soldered to. The lines from Apple’s fabric, which everything on the chip is connected with, extend to that substrate, to the RAM chips. Therefore, the RAM chips are separate from the SoC, and certainly not in the CPU itself.
As we also know, Apple offers several different levels of RAM for each M series they sell. That means that there is no limit to their ability to decide how much RAM they can offer, up to the number of memory lines that can be brought out. This is no different from any traditional computer. Every CPU and memory controller has a limit as to how much RAM can be used.
So, it seems to me that Apple could, if it wanted to, have sockets for those RAM packages, which add no latency, and would allow exchangeable RAM packages. Apple would just have to extend the maximum number of memory lines out to the socket. How many would get used would depend on the amount of RAM in the package. That’s nothing new. That’s how it’s done. Yes, under that scheme you would have to remove a smaller RAM package when getting a larger one, but that's also normal. The iMac had limited RAM slots and we used to do that all the time.
Apple could also add an extra two sockets, in addition to the RAM that comes with the machine. So possibly there would be two packages soldered to the substrate, and two more sockets for RAM expansion.
Remember that Apple sometimes does something a specific way, not because that’s the way it has to be done, but because they decided that this was the way they were going to do it. We don’t know where Apple is going with this in the future. It’s possible that the M2, which is really just a bump from the M1, is something to fill in the time while we’re waiting for the M3, which with the 3nm process it’s being built on, is expected to be more than just another bump in performance. Perhaps an extended RAM capability is part of that.
Yes. It is common knowledge that RAM is not part of the actual SoC, it's on package with the SoC. People use the term "SoC" to describe the whole part ("M1", "M2") which includes the RAM.
Being able to control how much RAM is installed allows Apple to guarantee that all memory channels are filled and being utilized, maximizing performance.
The article says: "Apple's M1 and M2 ARM-based chip designs are similar. They are essentially a SoC design that integrates CPUs, GPUs, main RAM, and other components into a single chip.".
That's ("... into a single chip") clearly incorrect for RAM. You may be able to squeak by with correct information by saying "main RAM, and other components into a SoC" where most of the, or many a, time when you say SoC, it's really short hand for "SoC package".
On the whole, mass media articles do a very poor job at delineating a chip from a package. It's not uncommon to read someone say Apple silicon machines have the RAM in the "chip". So, it does behoove us to get the media to make it more clear.
When compared to the current PC world, it is essentially one chip……..
Charging $200 for an 8GB RAM upgrade is not a "greed thing"? Charging $200 for a 256GB SSD upgrade is not a "greed thing"? Those are up to 10X the cost a PC user with modular upgrades pays. It most certainly is part greed. But then, Apple couldn't make that $3T valuation, could they?
No... it's not about greed... it's about performance per unit of energy... efficiency.
Those modular systems you like so well require twice as much battery to get half the performance and half the run-time.
If you don't care about efficiency (and that's perfectly acceptable.)... then by all means buy a modular system and heat your house with it.
So, it seems to me that Apple could, if it wanted to, have sockets for those RAM packages, which add no latency, and would allow exchangeable RAM packages. Apple would just have to extend the maximum number of memory lines out to the socket. How many would get used would depend on the amount of RAM in the package.
As long as Apple is using standard LPDDR memory, there isn't going to be any slotted RAM modules, The specification limits the max capacity to 8 GB, 16 GB per channel depending on LPDDR generation. Basically 1 LPDDR package per channel for every generation, and there is no point to having a slotted module in the specification for one package.
Each LPDDR memory channel has a "port" along the edges of the silicon chip. The M1 had 8 channels of LPDDR4 that takes basically 2 edges of the chip. So, they are butting against how many channels of LPDDR they can really add to the chips. They don't have much more room to add more channels per chip.
If they could get a next gen LPDDR version to support, say 64 GB per channel, they can hit 1 TB of memory on the Ultra by stacking 4 16 GB LPDDR packages per channel, or 2 32 GB LPDDR packages per channel. Kind of like an extension of specification that uses existing LPDDR5X or LPDDR6 designs, but it's probably not possible. It's important to get it into the specification so memory vendors can mass produce them for a wider variety of OEMs instead of a custom order for Apple, just for a commodity part.
No argument there. I’m saying that they can do it, and they can. But Apple has had custom memory before. They can get good pricing because of their size as a customer. As I said, it will be interesting where they take this in the M3 which is supposed to have major design upgrades.
Ok, so the writer gets it wrong, as so many others have when it comes to the M series RAM packaging. One would think that’s this simple thing would be well understood by now. So let me make it very clear - the RAM is NOT on the chip. It is NOT “in the CPU itself”. As we should all know by now, it’s in two packages soldered to the substrate, which is the small board the the SoC is itself soldered to. The lines from Apple’s fabric, which everything on the chip is connected with, extend to that substrate, to the RAM chips. Therefore, the RAM chips are separate from the SoC, and certainly not in the CPU itself.
As we also know, Apple offers several different levels of RAM for each M series they sell. That means that there is no limit to their ability to decide how much RAM they can offer, up to the number of memory lines that can be brought out. This is no different from any traditional computer. Every CPU and memory controller has a limit as to how much RAM can be used.
So, it seems to me that Apple could, if it wanted to, have sockets for those RAM packages, which add no latency, and would allow exchangeable RAM packages. Apple would just have to extend the maximum number of memory lines out to the socket. How many would get used would depend on the amount of RAM in the package. That’s nothing new. That’s how it’s done. Yes, under that scheme you would have to remove a smaller RAM package when getting a larger one, but that's also normal. The iMac had limited RAM slots and we used to do that all the time.
Apple could also add an extra two sockets, in addition to the RAM that comes with the machine. So possibly there would be two packages soldered to the substrate, and two more sockets for RAM expansion.
Remember that Apple sometimes does something a specific way, not because that’s the way it has to be done, but because they decided that this was the way they were going to do it. We don’t know where Apple is going with this in the future. It’s possible that the M2, which is really just a bump from the M1, is something to fill in the time while we’re waiting for the M3, which with the 3nm process it’s being built on, is expected to be more than just another bump in performance. Perhaps an extended RAM capability is part of that.
Actually, moving the memory further away from the CPU does add latency. Every foot of wire adds about a nanosecond of delay.
Then there is the issue of how many wires you run. When the memory is physically close to the CPU you can run more wires from the memory to the CPU, this allows you to get data to/from the CPU faster. It's not practical to run a large number of wires to a socket that might be a foot or more of cable run away. That means you transfer less data in each clock cycle.
Generally socketed memory is on an external bus. This lets various peripherals directly access memory. The bus arbitration also adds overhead.
Traditional CPUs try to overcome these memory bottlenecks by using multiple levels of cache. This can provide a memory bandwidth performance boost for chunks of recently accessed memory. However, tasks that use more memory than will fit in the cache, may not benefit from these techniques.
Apples "System on a Chip" design really does allow much higher memory bandwidth. Socketing the memory really would reduce performance.
We’re talking about no change in distance. The socket can be exactly where the RAM packages are now. If extra sockets are added, one on each side. We’re talking about 0.375”.
the way they do it now is to have one package on each side of the SoC. When they double packages, they put one slightly further down, and the other slightly higher. We’re talking about fractions of an inch from the way they add packages. There’s nothing really different here. Just substitute soldered on packages to low profile sockets. Not talking about going to DIMMs. The same packages they use now, but with pins instead of solder connections.
you’re talking about something entirely different, and it doesn’t apply. Sickest won’t change anything here.
How many pins would the socket need to accommodate the current chips? How reliable are those sockets? Are the current chips available in a socketable version?
It would depend on the amount of RAM. They’re pretty reliable as are all sockets these days. That’s not an issue. This is all custom designs from Apple. They don’t need standard anything. They have designed custom sockets before, and are using them for a number of things now.
So, it seems to me that Apple could, if it wanted to, have sockets for those RAM packages, which add no latency, and would allow exchangeable RAM packages. Apple would just have to extend the maximum number of memory lines out to the socket. How many would get used would depend on the amount of RAM in the package.
As long as Apple is using standard LPDDR memory, there isn't going to be any slotted RAM modules, The specification limits the max capacity to 8 GB, 16 GB per channel depending on LPDDR generation. Basically 1 LPDDR package per channel for every generation, and there is no point to having a slotted module in the specification for one package.
Each LPDDR memory channel has a "port" along the edges of the silicon chip. The M1 had 8 channels of LPDDR4 that takes basically 2 edges of the chip. So, they are butting against how many channels of LPDDR they can really add to the chips. They don't have much more room to add more channels per chip.
If they could get a next gen LPDDR version to support, say 64 GB per channel, they can hit 1 TB of memory on the Ultra by stacking 4 16 GB LPDDR packages per channel, or 2 32 GB LPDDR packages per channel. Kind of like an extension of specification that uses existing LPDDR5X or LPDDR6 designs, but it's probably not possible. It's important to get it into the specification so memory vendors can mass produce them for a wider variety of OEMs instead of a custom order for Apple, just for a commodity part.
No argument there. I’m saying that they can do it, and they can. But Apple has had custom memory before. They can get good pricing because of their size as a customer. As I said, it will be interesting where they take this in the M3 which is supposed to have major design upgrades.
They are obviously very cost conscious with their components. In hindsight, their 4 to 16 channels of LPDDR is the obvious solution to providing the most bandwidth as cheap as possible. So, if you can get into their heads, what memory implementation can they do that makes use of cheap mass produced memory components, the cheapest SoC package and the cheapest logic board solution while providing the most bandwidth? 8 channels of DDR5/6?
I think everyone and their second cousin were thinking they were going to use HBM. HBM3 can have up to 32 GB packages (currently no customer for a 16 hi HBM3 package I think). An M3 Max with 4 HBM3 packages would be 128 GB memory capacity with 3.2 TB/s bandwidth. It may enable linear performance scaling per core for their GPU. They just aren't going to do because it is too expensive and uses too much power.
So, it seems to me that Apple could, if it wanted to, have sockets for those RAM packages, which add no latency, and would allow exchangeable RAM packages. Apple would just have to extend the maximum number of memory lines out to the socket. How many would get used would depend on the amount of RAM in the package.
As long as Apple is using standard LPDDR memory, there isn't going to be any slotted RAM modules, The specification limits the max capacity to 8 GB, 16 GB per channel depending on LPDDR generation. Basically 1 LPDDR package per channel for every generation, and there is no point to having a slotted module in the specification for one package.
Each LPDDR memory channel has a "port" along the edges of the silicon chip. The M1 had 8 channels of LPDDR4 that takes basically 2 edges of the chip. So, they are butting against how many channels of LPDDR they can really add to the chips. They don't have much more room to add more channels per chip.
If they could get a next gen LPDDR version to support, say 64 GB per channel, they can hit 1 TB of memory on the Ultra by stacking 4 16 GB LPDDR packages per channel, or 2 32 GB LPDDR packages per channel. Kind of like an extension of specification that uses existing LPDDR5X or LPDDR6 designs, but it's probably not possible. It's important to get it into the specification so memory vendors can mass produce them for a wider variety of OEMs instead of a custom order for Apple, just for a commodity part.
No argument there. I’m saying that they can do it, and they can. But Apple has had custom memory before. They can get good pricing because of their size as a customer. As I said, it will be interesting where they take this in the M3 which is supposed to have major design upgrades.
They are obviously very cost conscious with their components. In hindsight, their 4 to 16 channels of LPDDR is the obvious solution to providing the most bandwidth as cheap as possible. So, if you can get into their heads, what memory implementation can they do that makes use of cheap mass produced memory components, the cheapest SoC package and the cheapest logic board solution while providing the most bandwidth? 8 channels of DDR5/6?
I think everyone and their second cousin were thinking they were going to use HBM. HBM3 can have up to 32 GB packages (currently no customer for a 16 hi HBM3 package I think). An M3 Max with 4 HBM3 packages would be 128 GB memory capacity with 3.2 TB/s bandwidth. It may enable linear performance scaling per core for their GPU. They just aren't going to do because it is too expensive and uses too much power.
I don’t think the cost is as much of an issue as the power. Apple could get pretty good pricing. All the reason I’m seeing against this is convenience, price, etc. none of it is technical. It can be done. As I’ve said, it’s just a matter of whether Apple would do it.
so, the question is what happened to the Mac Pro? Were they working on an Extreme version of the chip? If so, it shows that for higher end equipment, cost was t an object. They just couldn’t get that working. Maybe for the M3. But we’re still in the early stages here, about where Intel was with the 8080, so we shouldn’t be too locked into what we think Apple,can, or will do. They’re thinking ten years ahead here, and I somehow doubt it’s just iterations of what they have now.
Have you ever heard of broken cpu? Not the most common reason for computer to break down anuway.
And if it does, then you must replace it with new cpu as you must in any other architecture.
Didn’t buy that con also as i have strong guts that all in one chip is way more robust than the traditional way with separate bigger vomponents attached tohether.
Charging the customer a $200 upgrade fee for a component that costs them around $2 internally is great for Apple and their shareholders, but extremely bad for everyone else, including the greater tech economy as a whole.
There used to be a ton of hardware companies that made aftermarket Mac accessories and upgrades, that also employed collectively thousands of techs and engineers, and now they’re all selling phone cases, if they’re still in business at all that is.
Re: “What happened to the Mac Pro”
The yields from TSMC were terrible for the 4x fused SoCs, and the other problem was and still is workload scaling. It’s supposed to be “it just works” but it doesn’t. Even the 2x ultra chips in the Mac studios don’t scale linearly like they should. There are bottlenecks.
Also lots of misinformation in these posts. It’s entirely possible to have modular LPDDR, Micron just showed off LPCAMM2 off at CES. And there actually were quite a few dGPUs that had modular memory back in the day. Not the majority at all, but they absolutely did exist.
Comments
I think everyone and their second cousin were thinking they were going to use HBM. HBM3 can have up to 32 GB packages (currently no customer for a 16 hi HBM3 package I think). An M3 Max with 4 HBM3 packages would be 128 GB memory capacity with 3.2 TB/s bandwidth. It may enable linear performance scaling per core for their GPU. They just aren't going to do because it is too expensive and uses too much power.
so, the question is what happened to the Mac Pro? Were they working on an Extreme version of the chip? If so, it shows that for higher end equipment, cost was t an object. They just couldn’t get that working. Maybe for the M3. But we’re still in the early stages here, about where Intel was with the 8080, so we shouldn’t be too locked into what we think Apple,can, or will do. They’re thinking ten years ahead here, and I somehow doubt it’s just iterations of what they have now.
Didn’t buy that con also as i have strong guts that all in one chip is way more robust than the traditional way with separate bigger vomponents attached tohether.
There used to be a ton of hardware companies that made aftermarket Mac accessories and upgrades, that also employed collectively thousands of techs and engineers, and now they’re all selling phone cases, if they’re still in business at all that is.
Re: “What happened to the Mac Pro”
The yields from TSMC were terrible for the 4x fused SoCs, and the other problem was and still is workload scaling. It’s supposed to be “it just works” but it doesn’t. Even the 2x ultra chips in the Mac studios don’t scale linearly like they should. There are bottlenecks.
Also lots of misinformation in these posts. It’s entirely possible to have modular LPDDR, Micron just showed off LPCAMM2 off at CES. And there actually were quite a few dGPUs that had modular memory back in the day. Not the majority at all, but they absolutely did exist.