I've heard it said that two out of three ain't bad <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" /> </strong><hr></blockquote>
Raising clock speed slows down transistors and results in higher power requirements in a CMOS based design. A tweaked, 4 stage pipeline on top of a smartly designed system is probably, transistor for transistor, watt for watt, the fastest way.
"Raising clock speed slows down transistors and results in higher power requirements in a CMOS based design"
<img src="graemlins/oyvey.gif" border="0" alt="[No]" /> ok, you don't know what your talking about. To give you a little VLSI lesson:
there are three sources of power dissipation in a CMOS circuit:
1. Static power disipation caused by the parasitic diode. The leakage currend equation is:
Id = Is*[e^(9*V/kT)-1] and the power Ps = n*Id*Vdd where n is the number of devices. To lower static power dissipation, use a lower Vdd or fewer devices
2. Dynamic Power dissipation
this is caused by the capacitive charging and discharging in a circuit. The dynamic power dissipation is Pd = n*f*Cl*Vdd where n= number of devices, f = frequency, Cl is the load capacitance (dependant on fabrication technique, architecture, and physical layout) and Vdd is the rail to rail voltage. Power dissipation increases as frequency increases not because "raising clock speed slows down transistors", but because of increased capacative charging/discharging.
3.Short Circuit Power dissipation
caused when the pull-up (usually PMOS) and pull-down (n-mos) transistors are "on" at the same time. Psc = (f/12)[(Vdd - 2Vt)^3]*Cl/Vdd where Vt equals the threshold voltage. Again, increasing frequency doesn't "slow down transistors" causing increased power dissipation, what it does is cause a short circuit to occur more frequently per second, resulting in higher power dissipation.
As for your comments on a "tweaked 4 stage pipeline", well, Computer Architecture is far more complex, and to assume that a 4 stage pipeline is pound for pound fastest is a mistake, and just plain wrong given current technology. With your current course of education as a sophomore in EE at princeton, I imagine you're a bright kid... you'll learn a little about this stuff in the next 2 years... til then, wait till you know what you are talking about.
When I say that raising clock speed slows down transistors and increases power consumption, I am referring to the things you say. But to go in depth about it seemed pointless.
Yes, it's the dynamic power functionality of CMOS that makes frequency boosting power hungry. I'm going through a rather hellish semiconductor device physics class now where they beat this into our brains. I think I was off about the speed thing, but by increasing pipelines one increases transistor count, which increases fanouts, increasing delay. Either that or it just means a signal takes longer to go throught the circuit. In these respects I do know what I'm talking about. I see you're an almighty grad student, but aside from the 4-stage thing (see next paragraph) you haven't made any claim that shows that I'm incorrect. Rather you confirmed that higher clock speeds raise power consumption in a CMOS design. I'm a bit confused why you consider me to be so fully incorrect.
As for the 4 stage thing, that was mostly speculation based on what I've read from various journals here and there, but it seems true. I'm sure you know better than I, though.
But it remains that the primary reason for deepening the pipeline and raising the clock speed of the p4 was probably to increase marketability.
first and foremost - I mean no offense... second, my complaint was that your comment poorly represented the realities of VLSI and computer architecture. Increasing the number of pipeline stages: (generally)
1. increases instruction throughput (good thing)
2. can better balance stage delay (very good thing)
3. CAN increase instruction latency (a bad thing, though it is often worth it)...
increasing the number of stages in a pipline at first look only negligably increases transistor counts (not many transistors are needed to insert latches between stages), and again at first look - power dissipation. The problem reguarding power dissipation is this: as the frequency is scaled up due to the shorter pipeline stages, power usage increases. This can be ok, as long as the IPC (instructions per clock) doesn't suffer - the problem occurs when you have extremely deep pipelines, and memory/data or control hazards/dependancies cause stalls in the pipeline - this lowers the IPC dramatically, and as a result, more clock cycles are needed to execute the instructions. It is these wasted cycles burning power which are greatly responsible for the increased power requirements per instruction executed in the P4 vs. P3 and others (among many other things). To respond to this, more complex instruction re-ordering and branch prediction hardware must be used to compensate - ultimately leading to diminishing returns of increasing the pipeline depth. Another major problem with increasing the pipeline depth is that sequencing overhead of latches/flip-flops consume a higher percentage of eacy clock cycle, leaving less time for productive logic - also reducing the gains in extending the pipeline depth. The P4 is a very aggressive design in terms of increasing instruction throughput, reguardless if sacrafices were made to increase clock frequency or not.
you're correct when you say that marketing played a role in design decisions to deepen the P4 pipelines (it does in every chip...), though there are also quite valid reasons for it as well (disclaimer: I will very soon be employed at a large microprocessor company that is probably not liked much around here...). As far as the design of the G4... it has some very strong points, however, for a processor with such a clean instruction architecture, it is not a very agressive design for a desktop processor - much more could be done. It is a very balanced processor, with surprisingly good performance in certain areas, but as painful as it may be to hear, it is an embedded processor.
The bottom line is this: all engineering is a balencing act of tradeoffs. Do I spend more money for more performance? do I spend more engineering time for slightly better die size? ... and so on... The factors deciding what decisions must be made change rapidly, and are dictated by design goals, ie: performance, price, power usage, availability, compability...
Anyway, like I said earlier, you're probably a very bright kid, and I remember painfully my undergrad VLSI days... my response was instigated simply by a desire to prevent the often misinformed speculation on these boards...
The reality is (simplisticly) the more the transistors, the more the line resistance, the more power it takes to send the signal down the line. The smaller line width the smaller the resistance the smaller the power needed; increase the frequency more energy losses.
<strong>(disclaimer: I will very soon be employed at a large microprocessor company that is probably not liked much around here...)</strong><hr></blockquote>
pfft, Intel isn't that bad. Money is money and engineering is engineering. It's all in the competition.</strong><hr></blockquote>
Oh Intel is that bad, it's not competition for them, it's continuation of their monopolistic practices and strongarming of the industry. But that's just my opinion
[quote]Motorola's PowerPC G5 / 8500 processor may never arrive. A source who wishes not to be identified indicated to us that Motorola cancelled further development of the G5 chip over a year ago, and will concentrate on speeding up the G4 processor. By 2003, Apple is expected to use an IBM PowerPC chip for their fastest machines, while Motorola keeps selling them improved G4 chips for their iMacs and low-end. It's not clear yet what will happen to the AltiVec instruction set, or how that will be dealt with between Motorola and IBM. When we get more details, we will post them. For now, this is still all unconfirmed and should be treated as a rumor, but one that seems to make sense if you look at Motorola's tough financial situation, their focus on more profitable divisions, and the lack of further G5 details forthcoming from Motorola. <hr></blockquote>
Not saying I believe it either way, just a heads up on the new info...
If I was SteveJobs and Moto cancelled the G5. I would buy the rights to the PPC instruction set and Altivec and licence AMD to put it in the hammer or at least give IBM the Altivec licence.
Or, Perhaps Moto cancelled the G5, because they knew Apple was going to buy the PPC&Altivec IA, and give it to AMD/IBM.
But all this buying the PPC ISA rumour doesn't make sense when you think that Moto sells most of the PPC chips to other companies. Why would they give that up? Could they just licence/sell apple the right to buy the PPC ISA as it is to do whatever they wanted for the mac, while continuing to make their own PPC?
Comments
<strong>
I've heard it said that two out of three ain't bad <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" /> </strong><hr></blockquote>
Raising clock speed slows down transistors and results in higher power requirements in a CMOS based design. A tweaked, 4 stage pipeline on top of a smartly designed system is probably, transistor for transistor, watt for watt, the fastest way.
<img src="graemlins/oyvey.gif" border="0" alt="[No]" /> ok, you don't know what your talking about. To give you a little VLSI lesson:
there are three sources of power dissipation in a CMOS circuit:
1. Static power disipation caused by the parasitic diode. The leakage currend equation is:
Id = Is*[e^(9*V/kT)-1] and the power Ps = n*Id*Vdd where n is the number of devices. To lower static power dissipation, use a lower Vdd or fewer devices
2. Dynamic Power dissipation
this is caused by the capacitive charging and discharging in a circuit. The dynamic power dissipation is Pd = n*f*Cl*Vdd where n= number of devices, f = frequency, Cl is the load capacitance (dependant on fabrication technique, architecture, and physical layout) and Vdd is the rail to rail voltage. Power dissipation increases as frequency increases not because "raising clock speed slows down transistors", but because of increased capacative charging/discharging.
3.Short Circuit Power dissipation
caused when the pull-up (usually PMOS) and pull-down (n-mos) transistors are "on" at the same time. Psc = (f/12)[(Vdd - 2Vt)^3]*Cl/Vdd where Vt equals the threshold voltage. Again, increasing frequency doesn't "slow down transistors" causing increased power dissipation, what it does is cause a short circuit to occur more frequently per second, resulting in higher power dissipation.
As for your comments on a "tweaked 4 stage pipeline", well, Computer Architecture is far more complex, and to assume that a 4 stage pipeline is pound for pound fastest is a mistake, and just plain wrong given current technology. With your current course of education as a sophomore in EE at princeton, I imagine you're a bright kid... you'll learn a little about this stuff in the next 2 years... til then, wait till you know what you are talking about.
Yes, it's the dynamic power functionality of CMOS that makes frequency boosting power hungry. I'm going through a rather hellish semiconductor device physics class now where they beat this into our brains. I think I was off about the speed thing, but by increasing pipelines one increases transistor count, which increases fanouts, increasing delay. Either that or it just means a signal takes longer to go throught the circuit. In these respects I do know what I'm talking about. I see you're an almighty grad student, but aside from the 4-stage thing (see next paragraph) you haven't made any claim that shows that I'm incorrect. Rather you confirmed that higher clock speeds raise power consumption in a CMOS design. I'm a bit confused why you consider me to be so fully incorrect.
As for the 4 stage thing, that was mostly speculation based on what I've read from various journals here and there, but it seems true. I'm sure you know better than I, though.
But it remains that the primary reason for deepening the pipeline and raising the clock speed of the p4 was probably to increase marketability.
[ 04-28-2002: Message edited by: Splinemodel ]</p>
1. increases instruction throughput (good thing)
2. can better balance stage delay (very good thing)
3. CAN increase instruction latency (a bad thing, though it is often worth it)...
increasing the number of stages in a pipline at first look only negligably increases transistor counts (not many transistors are needed to insert latches between stages), and again at first look - power dissipation. The problem reguarding power dissipation is this: as the frequency is scaled up due to the shorter pipeline stages, power usage increases. This can be ok, as long as the IPC (instructions per clock) doesn't suffer - the problem occurs when you have extremely deep pipelines, and memory/data or control hazards/dependancies cause stalls in the pipeline - this lowers the IPC dramatically, and as a result, more clock cycles are needed to execute the instructions. It is these wasted cycles burning power which are greatly responsible for the increased power requirements per instruction executed in the P4 vs. P3 and others (among many other things). To respond to this, more complex instruction re-ordering and branch prediction hardware must be used to compensate - ultimately leading to diminishing returns of increasing the pipeline depth. Another major problem with increasing the pipeline depth is that sequencing overhead of latches/flip-flops consume a higher percentage of eacy clock cycle, leaving less time for productive logic - also reducing the gains in extending the pipeline depth. The P4 is a very aggressive design in terms of increasing instruction throughput, reguardless if sacrafices were made to increase clock frequency or not.
you're correct when you say that marketing played a role in design decisions to deepen the P4 pipelines (it does in every chip...), though there are also quite valid reasons for it as well (disclaimer: I will very soon be employed at a large microprocessor company that is probably not liked much around here...). As far as the design of the G4... it has some very strong points, however, for a processor with such a clean instruction architecture, it is not a very agressive design for a desktop processor - much more could be done. It is a very balanced processor, with surprisingly good performance in certain areas, but as painful as it may be to hear, it is an embedded processor.
The bottom line is this: all engineering is a balencing act of tradeoffs. Do I spend more money for more performance? do I spend more engineering time for slightly better die size? ... and so on... The factors deciding what decisions must be made change rapidly, and are dictated by design goals, ie: performance, price, power usage, availability, compability...
Anyway, like I said earlier, you're probably a very bright kid, and I remember painfully my undergrad VLSI days... my response was instigated simply by a desire to prevent the often misinformed speculation on these boards...
You going to be at Hillsboro or Satan Clara?
<strong>(disclaimer: I will very soon be employed at a large microprocessor company that is probably not liked much around here...)</strong><hr></blockquote>
You're going to work for Motorola?
<strong>
You're going to work for Motorola?
I thought he said microprocessor company?
[ 04-28-2002: Message edited by: Eskimo ]</p>
edit: not Via either...
[ 04-28-2002: Message edited by: grad student ]</p>
<strong>uh, in santa clara, and not motorola, and like I said... the company is not liked much round here... thanks for the congrats though...
</strong><hr></blockquote>
pfft, Intel isn't that bad. Money is money and engineering is engineering. It's all in the competition.
<strong>
I know, but try getting some of the 'I'm so cool because I pretend I'm important and know stuff' residents of these here forums to listen.
Barto
PS I think I'm going to use your post as my sig
[ 04-26-2002: Message edited by: Barto ]</strong><hr></blockquote>
Cool
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
you might want to edit a bit though.
[ 04-29-2002: Message edited by: Blackcat ]</p>
<strong>
pfft, Intel isn't that bad. Money is money and engineering is engineering. It's all in the competition.</strong><hr></blockquote>
Oh Intel is that bad, it's not competition for them, it's continuation of their monopolistic practices and strongarming of the industry. But that's just my opinion
<a href="http://www.geek.com/procspec/apple/g5.htm"; target="_blank">http://www.geek.com/procspec/apple/g5.htm</a>;
[quote]Motorola's PowerPC G5 / 8500 processor may never arrive. A source who wishes not to be identified indicated to us that Motorola cancelled further development of the G5 chip over a year ago, and will concentrate on speeding up the G4 processor. By 2003, Apple is expected to use an IBM PowerPC chip for their fastest machines, while Motorola keeps selling them improved G4 chips for their iMacs and low-end. It's not clear yet what will happen to the AltiVec instruction set, or how that will be dealt with between Motorola and IBM. When we get more details, we will post them. For now, this is still all unconfirmed and should be treated as a rumor, but one that seems to make sense if you look at Motorola's tough financial situation, their focus on more profitable divisions, and the lack of further G5 details forthcoming from Motorola. <hr></blockquote>
Not saying I believe it either way, just a heads up on the new info...
This would explain the deathly silence on the issue.
Surely they wouldn't cancel something they'd developed for such a long time?
It would explain its delay!!!
That leaves IBM to deliver...multicore solution?
What? Two g3 with simd unit stuck together?
I hope they got more fpus in there if so!
Hmmm.
Lemon Bon Bon <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
Or, Perhaps Moto cancelled the G5, because they knew Apple was going to buy the PPC&Altivec IA, and give it to AMD/IBM.
But all this buying the PPC ISA rumour doesn't make sense when you think that Moto sells most of the PPC chips to other companies. Why would they give that up? Could they just licence/sell apple the right to buy the PPC ISA as it is to do whatever they wanted for the mac, while continuing to make their own PPC?
<strong>G5 'cancelled' over a year ago?
That leaves IBM to deliver...multicore solution?
Lemon Bon Bon <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" /> </strong><hr></blockquote>
I dream of a kind of desktop version of the POWER4 with some sort of SIMD solution, of course, it's still a dream ...