CNet: Macs to drive on HyperTransport links
From CNet news...
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Quote:
Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.
The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said.
Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.
The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said.
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Comments
--------- ---------
| PPC 970 | | PPC 970 |
--------- ---------
| |
970 bus 970 bus
| |
----------- ----------
| System | Hyper | System |
PC3200 ---| ASIC |-- Transport --| ASIC |--- 4 GB PC3200
Unused AGP -| | | |--- AGP
----------- ----------
| |
HyperTransport HyperTransport
| |
~ --------
| South |
| bridge |
--------
Or this:
--------- ---------
| PPC 970 | | PPC 970 |
--------- ---------
| |
970 bus 970 bus
| |
----------- ----------
PC3200 ---| System | Hyper | System |--- PC3200
Unused AGP -| ASIC |-- Transport --| ASIC |--- AGP
Unused PCI -| | | |--- PCI ---|
----------- ---------- |
| | |
HyperTransport HyperTransport |
| | --------
~ ~ | South |
| bridge |
--------
Makes for a good way to add memory as processors are added.
Though it is interesting that they picked the name "Smeagol" for the OS revision that allows thee 970 to be compatible, because the whole idea behind HT is to allow all the chips to speak the same language so nothing has to be translated from chip to chip. "One bus to bind them" perhaps?
One bus to bind them
Either your thinking way to much into it or thats one hell of a coincidence
Makes for a good way to add memory as processors are added
Hmmm. So Hypertransport is a 'Gatekeeper'. Reduces the traditional 'inefficiency' of Dual Processor Systems like the 'power'Mac G4?
Arranged in parallel? Just stack another two on the sides and you have a quad system? Each 970 has its own self-contained 'roads' to AGP/memory etc? Direct Hypertransport 'ROWTING' (as you Americans say...) to reduce traditional 'dual' cpu system overheads? The 'Hypertransport' acts as a 'Ring Road' to each cpu? The Hypertransport 'road' is so WIDE that it reduces congestion by virtue of the fact that it can shift huge data thereby reduces 'congestion'? Parallel design...of 'self-contained' units which make it easier to add more 'mini-systems' in parallel to...with Hypertransport acting as the conduit to a very elegant solution? Hence the much longer and 'narrow' motherboard? (ie according to Macwhispers...) How long would a quad or Octo board be?
I'm trying to picture a quad system. Any chance you or someone could knock up a similar diagram but with four cpus instead?
I'm not technical...but I've got a picture in my head of what I think it looks like. I'm curious to see if I'm picturing it right...
More diagrams for Quad and Octo systems. I'm intrigued. You've awoken my 'visual eye'.
Lemon Bon Bon
Originally posted by Lemon Bon Bon
Hmmm. So Hypertransport is a 'Gatekeeper'. Reduces the traditional 'inefficiency' of Dual Processor Systems like the 'power'Mac G4?
The G4 SMP systems are fine. They can't handle more than 4 GB of memory, they are actually 36 bit systems but the software can only see 4 GB at a time, and the architecture performs about the same as any other architecture with only 2 processors and limited memory.
I'm trying to picture a quad system. Any chance you or someone could knock up a similar diagram but with four cpus instead?
I drew up a couple. It should be more obvious which would be more economical for Apple.
--------- ---------
| PPC 970 | | PPC 970 |
--------- ---------
| |
970 bus 970 bus
| |
----------- ----------
PC3200 ---| System | Hyper | System |--- PC3200
Unused AGP -| ASIC |-- Transport --| ASIC |--- AGP -------------
Unused PCI -| | | |--- PCI ----| Southbridge |
----------- ---------- -------------
| |
HyperTransport HyperTransport
| |
----------- ----------
PC3200 ---| System | Hyper | System |--- PC3200
Unused AGP -| ASIC |-- Transport --| ASIC |--- Unused AGP
Unused PCI -| | | |--- Unused PCI
----------- ----------
| |
970 bus 970 bus
| |
--------- ---------
| PPC 970 | | PPC 970 |
--------- ---------
or:
--------- ---------
| PPC 970 |--- ---| PPC 970 |
--------- | | ---------
| |
--------- ------------------- ---------
| PPC 970 |-----| ~~~~~~~~~~~~~~~ |-----| PPC 970 |
--------- | ~ L3 cache ~ | ---------
| ~~~~~~~~~~~~~~~ |
AGP bus ---| Switched Fabric |--- Lots of main memory
-------------------
|
Hypertransport
|
-------------
Ethernet ---| Southbridge |--- 1394
Audio ---| |--- USB
Wireless ---| |--- SATA
-------------
It would have even been cheaper if the 970 had Hypertransport links and a memory controller on-die because it would eliminate the need for more than 1 system ASIC for multiprocessor systems. On top of that, they then could have used AMD and Nvidia Hypertransport-based core logic chipsets much more easily.
On the otherhand, maybe Apple will surprise us and use Rambus! Or have 7 PCI slots or something.
With Hypertransport, Apple will finally catch up to modern technology. Still, don't expect any miracles in terms of beating Intel. There's a reason why Pixar went with Xeon's and didn't wait for the PPC970.
Originally posted by Existence
There's a reason why Pixar went with Xeon's and didn't wait for the PPC970.
Yup...they needed new computers *now*! Not a couple months later.
Originally posted by kim kap sol
Yup...they needed new computers *now*! Not a couple months later.
And the new computers were bought 13 months ago (I think the article in January made people think that PIXAR bought them in January).
Originally posted by keyboardf12
couldn't have anything to do with the fact that renderman has not been ported to OSX. nah.
Yet...
;^p
can't wait. not that i have a use for it, i just want to watch "knickknack" in realtime and twist it on its axis and watch it from diff. angles.
Originally posted by THT
The G4 SMP systems are fine. They can't handle more than 4 GB of memory, they are actually 36 bit systems but the software can only see 4 GB at a time, and the architecture performs about the same as any other architecture with only 2 processors and limited memory.
I drew up a couple. It should be more obvious which would be more economical for Apple.
Code:
--------- ---------
| PPC 970 | | PPC 970 |
--------- ---------
| |
970 bus 970 bus
| |
----------- ----------
PC3200 ---| System | Hyper | System |--- PC3200
Unused AGP -| ASIC |-- Transport --| ASIC |--- AGP -------------
Unused PCI -| | | |--- PCI ----| Southbridge |
----------- ---------- -------------
| |
HyperTransport HyperTransport
| |
----------- ----------
PC3200 ---| System | Hyper | System |--- PC3200
Unused AGP -| ASIC |-- Transport --| ASIC |--- Unused AGP
Unused PCI -| | | |--- Unused PCI
----------- ----------
| |
970 bus 970 bus
| |
--------- ---------
| PPC 970 | | PPC 970 |
--------- ---------
or:
--------- ---------
| PPC 970 |--- ---| PPC 970 |
--------- | | ---------
| |
--------- ------------------- ---------
| PPC 970 |-----| ~~~~~~~~~~~~~~~ |-----| PPC 970 |
--------- | ~ L3 cache ~ | ---------
| ~~~~~~~~~~~~~~~ |
AGP bus ---| Switched Fabric |--- Lots of main memory
-------------------
|
Hypertransport
|
-------------
Ethernet ---| Southbridge |--- 1394
Audio ---| |--- USB
Wireless ---| |--- SATA
-------------
It would have even been cheaper if the 970 had Hypertransport links and a memory controller on-die because it would eliminate the need for more than 1 system ASIC for multiprocessor systems. On top of that, they then could have used AMD and Nvidia Hypertransport-based core logic chipsets much more easily.
On the otherhand, maybe Apple will surprise us and use Rambus! Or have 7 PCI slots or something.
The diagram overlooks the cost benefits of using "jelly bean" functionally-focused HT bridges to go from the HT highway out to PCI-X, or AGP, or USB, etc. AMD already makes these. Mix and match.
Scaling system designs from lightweight to heavyweight becomes much easier if you are no longer forced to design kitchen sink ASICs due to bandwidth scarcity off chip. With HT you have plentiful bandwidth off chip so your hands are untied at the PCB level. Want a machine with two AGP ports (a power user feature)? Put another HT-AGP bridge chip on the highway, no ASIC redesign.
One could envision a chip that speaks 970-FSB, DRAM, and HT. For a dual processor config, just stack two copies of that same chip on the HT highway. No special MP ASIC for 2 way or 4 way. And in fact that would be the only 970-specific ASIC flavor on the board.
Originally posted by Existence
The current dual processor G4 machines Apple sells all used a shared bus topology. That means you have both G4's stuck sharing that 166MHz Mpx bus and 1.3GBps. No modern PC still uses shared bus topology. Intel Xeon's have independent busses to main memory for each processor.
Not quite. The Xeons *do* have a shared bus (as indeed, does the Itanium) currently peaking at 533MT/s. AMD's Athlon MPs, however, have independent busses.
michael
I was off about the HT vs RapidIO only because IBM and Modorolla both are on that standards committee and the switched fabric architecture seemed faster after my intense reading on the subject.
But Hypertransport Switching is possible now if I remember correctly, vastly enhancing everything about it.
As for available chips, AMD produced (when that post was written) an I/O Hub (basically a Southbridge), AGP3 tunnel, and PCI-X tunnel.
As interprocessor connect, AMD developed its own additions to HT for interprocessor connects. Can't remember the name off the top of my head.
Your mocks ups seem reasonable with the fact that the 970 doesn't have HT or memory controller.
Originally posted by THT
It would have even been cheaper if the 970 had Hypertransport links and a memory controller on-die because it would eliminate the need for more than 1 system ASIC for multiprocessor systems. On top of that, they then could have used AMD and Nvidia Hypertransport-based core logic chipsets much more easily.
I'd pretty much count on getting your wish when the 970's follow up appears since the memory controler will indeed be moved on chip.
Originally posted by wmf
Keep in mind that CNet doesn't know what they're talking about in general.
And their advertising is shear torture (to anyone waiting impatiently for Apple to release a Tablet).
Aries 1B
Originally posted by macserverX
Hypertransport Switching is possible now if I remember correctly, vastly enhancing everything about it.
HyperTransport will allow for serial, tree, switch (like NUMA) or even a mix and match of those topogies.
That is Apple could use a single serial HyperTransport chain for I/O.
While using a switch for multiprocessing.
And maybe another chain for memory.
However, i suspect that to begin with Apple will use just the one HyperTransport chain for simplicity of motherboard design. Later on perhaps with the introduction of the PPC 980 which is likely to add a second Apple PI BUS (HyperTransport derivative) connect and maybe even a direct memory controller/bus, Apple may advance the motherboard bus topology: switch for MP, serial for I/O and dedicated custom memory bus.