I've a question about Hypertransport and graphics cards. If an HT bus is available on the next PMac, can a graphics card be fitted to talk on that bus directly vs using AGP? (Obviously, I'm not too much into MB hardware). So instead of people wishing for 8x AGP, there is a new HT slot that ATI and nVidia build there card for specifically. How does it work?
<strong>Who is Grüne Hölle, and why do you want him to die? </strong><hr></blockquote>
This was covered in another thread, which I'm too lazy to look up.
Briefly, Grüne Hölle was a direct descendent of Genghis Khan (through his son Ögödei) whose band of masked marauders terrorized feudal Europe during the medieval times. But while Hölle's men pillaged and raped and maimed and hacked and slashed their way into the fears of all mankind, their story was lost for all eternity through a clerical error and a bad floppy disk.
From how I understand those isn't there a point where adding mhz doesn't make much sense because of the slow (?) bus? Or is that only a problem with huge data chunks in which case the bus was a problem before today already?</strong><hr></blockquote>
This leads me to a technical question, which hopefully somebody could answer for me. Which of the following would be better:
a 64-bit wide, 266 Mhz bus (ie, the DDR implementation of the current bus)
a 128-bit wide, 133 Mhz bus
or (just for comparison's sake) a 16-bit wide, 1 Ghz bus?
They all theoretically have the same throughput (2.1 GB/s), so what are the advantages of wider versus narrower?
<strong>I've a question about Hypertransport and graphics cards. If an HT bus is available on the next PMac, can a graphics card be fitted to talk on that bus directly vs using AGP? (Obviously, I'm not too much into MB hardware). So instead of people wishing for 8x AGP, there is a new HT slot that ATI and nVidia build there card for specifically. How does it work?</strong><hr></blockquote>
There are a number of ways HT could be used, but the most obvious is for a new processor to have an HT port to connect it to the chipset (instead of using the MPX bus). Another possibility, already used by nVidia's nForce chipset, is to connect the two chips which make up the chipset. Given that Apple is going to higher levels of integration, however, I suspect that they want to have just the processor(s) and a single chip I/O system. The memory controller would sit on one or the other. The I/O chip would contain the AGP bus controller.
Since nVidia and ATI are signed up to HT, it is possible that they will design versions of their hardware that talk HT. Currently there is no socket defined for HT, but that can likely be remedied with no major problems.
This is all speculation, of course, since no products have been announced yet.
FYI: a narrower bus is easier to build into the motherboard and connect chips to (fewer traces, fewer pins). Due to the reduction in cross-talk between the lines of the bus, they can typically be run at higher clock rates. The extreme is a serial bus, which has two lines (one in each direction) and can run at high rates. RamBus, HyperTransport and RapidIO all use the idea of a narrow, very fast bus.
Comments
<strong>Who is Grüne Hölle, and why do you want him to die? </strong><hr></blockquote>
This was covered in another thread, which I'm too lazy to look up.
Briefly, Grüne Hölle was a direct descendent of Genghis Khan (through his son Ögödei) whose band of masked marauders terrorized feudal Europe during the medieval times. But while Hölle's men pillaged and raped and maimed and hacked and slashed their way into the fears of all mankind, their story was lost for all eternity through a clerical error and a bad floppy disk.
And the rest, children, is iMac history.
<strong>
From how I understand those isn't there a point where adding mhz doesn't make much sense because of the slow (?) bus? Or is that only a problem with huge data chunks in which case the bus was a problem before today already?</strong><hr></blockquote>
This leads me to a technical question, which hopefully somebody could answer for me. Which of the following would be better:
a 64-bit wide, 266 Mhz bus (ie, the DDR implementation of the current bus)
a 128-bit wide, 133 Mhz bus
or (just for comparison's sake) a 16-bit wide, 1 Ghz bus?
They all theoretically have the same throughput (2.1 GB/s), so what are the advantages of wider versus narrower?
<strong>I've a question about Hypertransport and graphics cards. If an HT bus is available on the next PMac, can a graphics card be fitted to talk on that bus directly vs using AGP? (Obviously, I'm not too much into MB hardware). So instead of people wishing for 8x AGP, there is a new HT slot that ATI and nVidia build there card for specifically. How does it work?</strong><hr></blockquote>
There are a number of ways HT could be used, but the most obvious is for a new processor to have an HT port to connect it to the chipset (instead of using the MPX bus). Another possibility, already used by nVidia's nForce chipset, is to connect the two chips which make up the chipset. Given that Apple is going to higher levels of integration, however, I suspect that they want to have just the processor(s) and a single chip I/O system. The memory controller would sit on one or the other. The I/O chip would contain the AGP bus controller.
Since nVidia and ATI are signed up to HT, it is possible that they will design versions of their hardware that talk HT. Currently there is no socket defined for HT, but that can likely be remedied with no major problems.
This is all speculation, of course, since no products have been announced yet.
FYI: a narrower bus is easier to build into the motherboard and connect chips to (fewer traces, fewer pins). Due to the reduction in cross-talk between the lines of the bus, they can typically be run at higher clock rates. The extreme is a serial bus, which has two lines (one in each direction) and can run at high rates. RamBus, HyperTransport and RapidIO all use the idea of a narrow, very fast bus.