That would work for me. As nifty as a dedicated DSP on the memory controller might be in theory, it has a good chance of getting orphaned, like the DSP in the old AV series. Or IBM's ill-starred MicroChannel architecture.
I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.
I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.</strong><hr></blockquote>
Ah, so we are going to be disappointed again? So you think it will be MWSF before anything really juicy comes? I'm eager to ebay my dual gig when the next big thing comes out, but not for a gapper upgrade.
I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.</strong><hr></blockquote>
Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.
I thought that Trinity was the name of the lead female character in "The Matrix." So, hopefully we'll be getting an Altivec-enhanced Matrix screensaver from Apple at MWNY '02. </strong><hr></blockquote>
Sorry, but it's been "conformed" that this screensaveer has been postponed until MWSF '03.
"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."
The Greek god Apollo sometimes appeared as a Dolphin in order to "navigate people to his oracle".
dolphin = G4 Apollo(?)
AIM hasn't really gone away, so how can it return? The Cube has gone away but:
Cube ? returns after Pipeline Instructions, more voluminous than a G4 Apollo.
I could see an easy prediction for faster FSB implementation for Apollo's successor (G5 or G4), and in a new case (Cube), but my gut feeling is that, (assuming there is a valid rumor here) it would be more of a revelation than this.
<strong>I thought that Trinity was the name of the lead female character in "The Matrix." So, hopefully we'll be getting an Altivec-enhanced Matrix screensaver from Apple at MWNY '02. </strong><hr></blockquote>
Trinity was also the codename for the QuakeIII engine developed by iD software.
Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.
</strong><hr></blockquote>
Apple Computer confirmed today that CEO Steve Jobs will deliver his July keynote address from behind a 3" shield of bulletproof plexiglass, from which he is expected to announce upgrades to Apple's hardware, including its line of professional systems. A company spokesperson said only that the company has "credible information" about a possible threat to Jobs' life. Apple's online user community was quick to react, dubbing the new safety measure the "iShield" and "RDF 2.0."
In an unrelated story, today Apple also unveiled its latest marketing effort, "The Bandwidth Myth." Jobs is expected to explain this effort more fully in his keynote address.
<strong>I read in February I think about 'looking to someone rather then MOTO for Apple's next chip". Basically saying IBM was going to do it. So there seems to be a lot of sharing of the same sentiment that IBM will be doing Apple's next chip.</strong><hr></blockquote>
yeah, i originally said that. i didn't realize i was using such cryptic language. but if you search for it i said that right around february or so.
Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.
D</strong><hr></blockquote>
What I meant was that the new mobo with things like USB 2, 800mbps FireWire, 4 on-controller DSPs, DDR, etc. is still hung up with production issues. It was supposed to be out about 8 months ago, but it still isn't ready.
So instead, there will be a less ambitious DDR motherboard, with speedbumped G4's I'd imagine. I realize it may seem like a small upgrade, but the reality is that a faster bus will make a rather substantial difference in performance for many operations.
People who are claiming that the DDR implementation in the Xserve isn't "real" aren't understanding the issues. The DDR implementation is full-on DDR from the memory controller to system memory. The processor bus is already way faster than system memory anyway, so the DDR implementation in the Xserve and also in the upcoming G4 towers does indeed make a performance difference.
I don't expect that the alliance with IBM, if there is one will bear fruit for another year or so. Until then, speed bumped G4's and better motherboards is likely what you'll see.
<strong>Getting back to Apple 3.1415 (pi) (pie) whatever...
Remember back pre-MWSF and we had those criptic messages from Codename?
Well here was one of his messages:
"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."
No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...
Oh well... as you were..
Dave</strong><hr></blockquote>
it was probably related. i heard the term pi used in reference to this right around then. and it was referred to in the past tense, so the info was already out there.
People who are claiming that the DDR implementation in the Xserve isn't "real" aren't understanding the issues. The DDR implementation is full-on DDR from the memory controller to system memory. The processor bus is already way faster than system memory anyway, so the DDR implementation in the Xserve and also in the upcoming G4 towers does indeed make a performance difference.
</strong><hr></blockquote>
How is the current processor bus faster than DDR memory? It only runs at a SDR 133 Mhz, whereas PC 2100 DDR Memory is, well, DDR 133 Mhz. It provides twice the bandwidth than what the processor is capable of accessing because of its limited bus capacity.
No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...
How is the current processor bus faster than DDR memory? It only runs at a SDR 133 Mhz, whereas PC 2100 DDR Memory is, well, DDR 133 Mhz. It provides twice the bandwidth than what the processor is capable of accessing because of its limited bus capacity.</strong><hr></blockquote>
You're confusing the system bus with the processor bus.
No, you're confusing them, unfortunately.</strong><hr></blockquote>
As shown above, they are two different things.
It is my understanding that the 133mhz processor bus, depicted above, is *not* limited to 133mhz (in future mobo's), and thus the use of DDR will indeed be quite fortunate.
If you have information to the contrary, I'd love to hear it...
It is my understanding that the 133mhz processor bus, depicted above, is *not* limited to 133mhz (in future mobo's), and thus the use of DDR will indeed be quite fortunate.
If you have information to the contrary, I'd love to hear it...</strong><hr></blockquote>
I am talking about the G4 systems that are currently available. Including the DDR Xserve. What you call "System Bus" cannot run at more than what the processor supports. In the case of current G4s, they support 100 and 133 Mhz 64 bit busses, single data rate.
If you're saying that you have positive information that future (MWNY?) motherboards will use a faster bus, this means they will use a different (new and improved) G4. Which is great news and what we've been hoping for.
I am talking about the G4 systems that are currently available. Including the DDR Xserve. What you call "System Bus" cannot run at more than what the processor supports. In the case of current G4s, they support 100 and 133 Mhz 64 bit busses, single data rate.
If you're saying that you have positive information that future (MWNY?) motherboards will use a faster bus, this means they will use a different (new and improved) G4. Which is great news and what we've been hoping for.</strong><hr></blockquote>
If I had *positive* news on anything, I'd be under NDA. However, my understanding is that the DDR support in the new mobo does a significant job in increasing bus bandwidth, and I fail to see how that is possible unless the Maxbus supports either high speeds or accessing on both the up and down cycle of the bus, ala DDR.
I do know that the current 7450 supports DDR access to L3 Cache RAM, perhaps it supports it via Maxbus (the processor bus) as well? I've been looking over the PDFs at MOT to see for sure:
<strong>I need more information! Additionally, can anyone else confirm that Power5 and Power6 chips are being developed?</strong><hr></blockquote>
Even if there is no posted information (though they have made comments to release schedules) I can tell you from an engineering point of view and the development times involved they are already in development. Just don't ask me what they are developing as I don't work for IBM, although I have a friend who does.
I don't expect that the alliance with IBM, if there is one will bear fruit for another year or so. Until then, speed bumped G4's and better motherboards is likely what you'll see.</strong><hr></blockquote>
So we'll see the G4's successor in MWSF next year?
Comments
<strong>
That would work for me. As nifty as a dedicated DSP on the memory controller might be in theory, it has a good chance of getting orphaned, like the DSP in the old AV series. Or IBM's ill-starred MicroChannel architecture.
[ 06-11-2002: Message edited by: Amorph ]</strong><hr></blockquote>
I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.
<strong>
I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.</strong><hr></blockquote>
Ah, so we are going to be disappointed again? So you think it will be MWSF before anything really juicy comes? I'm eager to ebay my dual gig when the next big thing comes out, but not for a gapper upgrade.
<strong>
I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.</strong><hr></blockquote>
Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.
D
<strong>Amorph said:
I thought that Trinity was the name of the lead female character in "The Matrix." So, hopefully we'll be getting an Altivec-enhanced Matrix screensaver from Apple at MWNY '02.
Sorry, but it's been "conformed" that this screensaveer has been postponed until MWSF '03.
The Greek god Apollo sometimes appeared as a Dolphin in order to "navigate people to his oracle".
dolphin = G4 Apollo(?)
AIM hasn't really gone away, so how can it return? The Cube has gone away but:
Cube ? returns after Pipeline Instructions, more voluminous than a G4 Apollo.
I could see an easy prediction for faster FSB implementation for Apollo's successor (G5 or G4), and in a new case (Cube), but my gut feeling is that, (assuming there is a valid rumor here) it would be more of a revelation than this.
<strong>I thought that Trinity was the name of the lead female character in "The Matrix." So, hopefully we'll be getting an Altivec-enhanced Matrix screensaver from Apple at MWNY '02.
Trinity was also the codename for the QuakeIII engine developed by iD software.
<strong>
Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.
</strong><hr></blockquote>
Apple Computer confirmed today that CEO Steve Jobs will deliver his July keynote address from behind a 3" shield of bulletproof plexiglass, from which he is expected to announce upgrades to Apple's hardware, including its line of professional systems. A company spokesperson said only that the company has "credible information" about a possible threat to Jobs' life. Apple's online user community was quick to react, dubbing the new safety measure the "iShield" and "RDF 2.0."
In an unrelated story, today Apple also unveiled its latest marketing effort, "The Bandwidth Myth." Jobs is expected to explain this effort more fully in his keynote address.
*Appropriately with Apple's new iCam app and device.
Screed
[ 06-12-2002: Message edited by: sCreeD ]</p>
<strong>I read in February I think about 'looking to someone rather then MOTO for Apple's next chip". Basically saying IBM was going to do it. So there seems to be a lot of sharing of the same sentiment that IBM will be doing Apple's next chip.</strong><hr></blockquote>
yeah, i originally said that. i didn't realize i was using such cryptic language. but if you search for it i said that right around february or so.
<strong>
Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.
D</strong><hr></blockquote>
What I meant was that the new mobo with things like USB 2, 800mbps FireWire, 4 on-controller DSPs, DDR, etc. is still hung up with production issues. It was supposed to be out about 8 months ago, but it still isn't ready.
So instead, there will be a less ambitious DDR motherboard, with speedbumped G4's I'd imagine. I realize it may seem like a small upgrade, but the reality is that a faster bus will make a rather substantial difference in performance for many operations.
People who are claiming that the DDR implementation in the Xserve isn't "real" aren't understanding the issues. The DDR implementation is full-on DDR from the memory controller to system memory. The processor bus is already way faster than system memory anyway, so the DDR implementation in the Xserve and also in the upcoming G4 towers does indeed make a performance difference.
I don't expect that the alliance with IBM, if there is one
<strong>Getting back to Apple 3.1415 (pi) (pie) whatever...
Remember back pre-MWSF and we had those criptic messages from Codename?
Well here was one of his messages:
"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."
No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...
Oh well... as you were..
Dave</strong><hr></blockquote>
it was probably related. i heard the term pi used in reference to this right around then. and it was referred to in the past tense, so the info was already out there.
<strong>
People who are claiming that the DDR implementation in the Xserve isn't "real" aren't understanding the issues. The DDR implementation is full-on DDR from the memory controller to system memory. The processor bus is already way faster than system memory anyway, so the DDR implementation in the Xserve and also in the upcoming G4 towers does indeed make a performance difference.
</strong><hr></blockquote>
How is the current processor bus faster than DDR memory? It only runs at a SDR 133 Mhz, whereas PC 2100 DDR Memory is, well, DDR 133 Mhz. It provides twice the bandwidth than what the processor is capable of accessing because of its limited bus capacity.
No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...
</strong><hr></blockquote>
What exactly is/was 'Rosetta'?
<strong>
How is the current processor bus faster than DDR memory? It only runs at a SDR 133 Mhz, whereas PC 2100 DDR Memory is, well, DDR 133 Mhz. It provides twice the bandwidth than what the processor is capable of accessing because of its limited bus capacity.</strong><hr></blockquote>
You're confusing the system bus with the processor bus.
<strong>
You're confusing the system bus with the processor bus.</strong><hr></blockquote>
No, you're confusing them, unfortunately.
<strong>
No, you're confusing them, unfortunately.</strong><hr></blockquote>
As shown above, they are two different things.
It is my understanding that the 133mhz processor bus, depicted above, is *not* limited to 133mhz (in future mobo's), and thus the use of DDR will indeed be quite fortunate.
If you have information to the contrary, I'd love to hear it...
<strong>
As shown above, they are two different things.
It is my understanding that the 133mhz processor bus, depicted above, is *not* limited to 133mhz (in future mobo's), and thus the use of DDR will indeed be quite fortunate.
If you have information to the contrary, I'd love to hear it...</strong><hr></blockquote>
I am talking about the G4 systems that are currently available. Including the DDR Xserve. What you call "System Bus" cannot run at more than what the processor supports. In the case of current G4s, they support 100 and 133 Mhz 64 bit busses, single data rate.
If you're saying that you have positive information that future (MWNY?) motherboards will use a faster bus, this means they will use a different (new and improved) G4. Which is great news and what we've been hoping for.
<strong>
I am talking about the G4 systems that are currently available. Including the DDR Xserve. What you call "System Bus" cannot run at more than what the processor supports. In the case of current G4s, they support 100 and 133 Mhz 64 bit busses, single data rate.
If you're saying that you have positive information that future (MWNY?) motherboards will use a faster bus, this means they will use a different (new and improved) G4. Which is great news and what we've been hoping for.</strong><hr></blockquote>
If I had *positive* news on anything, I'd be under NDA. However, my understanding is that the DDR support in the new mobo does a significant job in increasing bus bandwidth, and I fail to see how that is possible unless the Maxbus supports either high speeds or accessing on both the up and down cycle of the bus, ala DDR.
I do know that the current 7450 supports DDR access to L3 Cache RAM, perhaps it supports it via Maxbus (the processor bus) as well? I've been looking over the PDFs at MOT to see for sure:
<a href="http://search.motorola.com/semiconductors/query.html?qt=g4+maxbus"; target="_blank">http://search.motorola.com/semiconductors/query.html?qt=g4+maxbus</a>;
[quote]For superior cache performance and reliability, the
MPC7450 adds DDR SRAM support and address
parity on the L3 bus. The MPC750 interfaces only
to synchronous burst SRAMs or late-write SRAMs
on the L2 bus and does not support L2 address
parity.
.....
Note that an upgrade from the MPC750 at 100MHz
to a MPC74xx at 133MHz can produce a sustained
system bus bandwidth improvement of more than
3x.
<hr></blockquote>
This is all old information, of course.
[ 06-12-2002: Message edited by: moki ]</p>
<strong>I need more information! Additionally, can anyone else confirm that Power5 and Power6 chips are being developed?</strong><hr></blockquote>
Even if there is no posted information (though they have made comments to release schedules) I can tell you from an engineering point of view and the development times involved they are already in development. Just don't ask me what they are developing as I don't work for IBM, although I have a friend who does.
<strong>
I don't expect that the alliance with IBM, if there is one
So we'll see the G4's successor in MWSF next year?