CONFIRMED: G5 enters volume production!

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  • Reply 161 of 239
    Like I said, Moki knows nothing.



  • Reply 162 of 239
    mokimoki Posts: 551member
    [quote]Originally posted by Nostradamus:

    <strong>Like I said, Moki knows nothing.

    </strong><hr></blockquote>



    Someone sounds a tad... spiteful.



    I'm perfectly willing to (once again) let history be my judge.
  • Reply 163 of 239
    outsideroutsider Posts: 6,008member
    OH, I get it! By showing me that picture (one that I have seen several times already) it has explained why moki knows nothing. It's all clear to me now. Thanks buddy!
  • Reply 164 of 239
    telomartelomar Posts: 1,804member
    History says moki often knows a lot more than people give him credit for or at least makes some awfully good guesses.



    He's also considerably more polite than some posters.



    Edit: Start of the message got garbled. Odd.



    [ 06-12-2002: Message edited by: Telomar ]</p>
  • Reply 165 of 239
    programmerprogrammer Posts: 3,467member
    Well here are the "facts" that I'm aware of (plus one supposition), and I think they explain what everybody is saying even though the end result still isn't as happy as a G5 w/ on-chip memory controller....



    - Moto's head of PPC development has said that MPX will not be significantly changed because the embedded customers are very happy with it and compatibility doesn't want to become an issue. A speed bump to 166 MHz is possible at some unspecified point in time. This means no DDR MPX, and maximum of 1.3 GB/sec.



    - Current PowerMacs achieve ~800 MB/sec in practice under very optimized circumstances. This is about 80% efficiency, which is remarkable from SDRAM who's theoretical peak is ~1 GB/sec. Usually it is more like 700 MB/sec or so.



    - Moki says that the DDR motherboard will deliver a bandwidth improvement.



    - Apple's Xserve propoganda claims 1 GB/sec to the processors. If this is a theoretical peak number, then its the same as the current PowerMacs. If it is an achieveable sustained number then it is ~20-25% better.



    - In the current machines we don't actually know if MPX imposes a 20-25% overhead, or if instead the memory controller and SDRAM itself imposes a 20-25% overhead.



    - DDR266/333 are more than 25% faster than SDRAM.



    - Here's the supposition: if MPX is zero overhead (and it might be, its a very cool protocol -- those embedded guys are happy about something!) then if you eliminate the overhead from the SDRAM and/or memory controller you have improved bandwidth by 20-25%. Not earth-shaking, but certainly notable. If on top of that you deliver a 166MHz version then you have improved memory bandwidth by 50+%, and you have a REAL 1.5 GB/sec -- compared to much higher theoretical numbers on the PC side of things. The better PCs out there still beat it, but at least we're making progress.



    Add to this the left over DDR bandwidth (if there is any) which will be consumed by the AGP reads from the GPU (thanks to Quartz Extreme) and the DMA activity from other devices, and the apparent performance increase over today's machines is even greater.



    Not entirely implausible, if I do say so myself.



    [ 06-12-2002: Message edited by: Programmer ]</p>
  • Reply 166 of 239
    frawgzfrawgz Posts: 547member
    [quote]Originally posted by Big Mac:

    <strong>Great performance isn't a luxury in the computer space, especially with Intel making the gains it has made in the last couple of years. If the SPEC numbers I've seen posted here are to be believed, then the P4 is catching up to the Power4, which is currently the fastest processor money can buy. If that's the case, then we all must worry, since our G4 will be blown out of the water if the new P4s are posting those kinds of numbers. (It's disheartening to notice that no one bothers to even post SPEC numbers for the G4 anymore.)</strong><hr></blockquote>



    Hehe

  • Reply 166 of 239
    zazzaz Posts: 177member
    OK, wait a second...



    Has anyone actually tested an Xserve and is anyone well informed as to its real memory performance...?



    Or is all this conjecture and dubbing of the Xserve DDR system a 'hack' and 'ineffective' interpolation of Jobs' Slide show?



    Until we see some hard numbers this whole 'down on Xserve DDR hackery' seems like a lot of hot air.



    Sure it would be better with a revised G4, etc..



    ..but better than what?
  • Reply 168 of 239
    ptrashptrash Posts: 296member
    I've read many times that a major reason graphics pros stick with Macs is because they have so much cash invested in the software. (It's true for me at my job even though I'm not a pro, that and also because all the designers I know use Macs and I need to be compatible) Now, with OSX having "arrived" eventually new software coming out will no longer support OS 9. So, if graphics pros are going to have to make major investments in new software over the next year or so, and with Apple's current generation hardware falling more and more behind the PC platform's, it seems like the time is coming when it may make sense for these people to make the switch. Especially if Apple has no next generation processor, or if their next gen version takes so long to come out that it's no longer next gen!



    It may be the ultimate irony: the OS that Apple thought would save the day, or even increase their market share, actually does them in (in combination with their fouled up hardware situation).
  • Reply 169 of 239
    Wow, the Pentium IV ownz the Power4!



    Intel really is brilliant at building CPUs. It's difficult to imagine how Apple is ever going to offer competitive hardware unless they use x86. In a few years, the Pentium is going to be so much faster than any PPC, that Apple may as well be selling abacuses.
  • Reply 170 of 239
    zazzaz Posts: 177member
    Maybe someone can correct me, but wasn't the Power4 that was tested a single cpu core version as opposed to its actual 2 cpu core?
  • Reply 171 of 239
    bartobarto Posts: 2,246member
    [quote]Originally posted by Junkyard Dawg:

    <strong>Wow, the Pentium IV ownz the Power4!



    Intel really is brilliant at building CPUs. It's difficult to imagine how Apple is ever going to offer competitive hardware unless they use x86. In a few years, the Pentium is going to be so much faster than any PPC, that Apple may as well be selling abacuses.</strong><hr></blockquote>



    The trouble with Junkyard Dawg is that you never know whether or not it is being sarcastic.



    Moki, most people here respect you with the exeption of some forum goers who have brains too small to be able to respect the fact that we have someone with a bit of knowledge posting at these boards.



    Barto
  • Reply 172 of 239
    thttht Posts: 5,605member
    <strong>Originally posted by Junkyard Dawg:

    Wow, the Pentium IV ownz the Power4!</strong>



    Those are integer numbers. The Power4 floating point numbers are 50% better than a P4. Moreover, it'll be stupid to compare the processors since Power4 is built for server usage while the P4 is built for consumer usage. Their domains really don't overlap much if at all.



    <strong>Intel really is brilliant at building CPUs. It's difficult to imagine how Apple is ever going to offer competitive hardware unless they use x86. In a few years, the Pentium is going to be so much faster than any PPC, that Apple may as well be selling abacuses.</strong>



    No doubt that Intel is excellent at design x86 processors. However and more importantly, Intel is the best processor manufacturer out there. Best option is for Apple to design its own PPC processors and have Intel fabricate them. Intel will be ahead of everyone else in getting to 0.09u and smaller fabs. They are virtually the only company that can afford it.
  • Reply 173 of 239
    mokimoki Posts: 551member
    [quote]Originally posted by frawgz:

    <strong>



    Hehe

    (graph deleted)</strong><hr></blockquote>



    Sure, until the 2.4ghz Xeon and the 2.5ghz P4, the POWER4 was the undisputed champ compared to the 2.2ghz P4 (the next closest contendor).



    Take a look at the floating point performance, though -- the POWER4 is still the champ by a good margin:



    <a href="http://www.ideasinternational.com/benchmark/spec/specfp_s2000.html"; target="_blank">http://www.ideasinternational.com/benchmark/spec/specfp_s2000.html</a>;



    That's pretty impressive for a chip that is almost half the clockspeed -- imagine how it will do at 2ghz or so, using a .13 micron process (or even a .9 micron process and yet higher clockspeeds).



    The POWER4 has legs, folks.



    [ 06-13-2002: Message edited by: moki ]</p>
  • Reply 174 of 239
    mokimoki Posts: 551member
    [quote]Originally posted by zaz:

    <strong>Maybe someone can correct me, but wasn't the Power4 that was tested a single cpu core version as opposed to its actual 2 cpu core?</strong><hr></blockquote>



    It is a single core (two CPUs per core) -- having two CPUs working in tandem per core is inherent to the POWER4 architecture:



    <a href="http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.html"; target="_blank">http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.html</a>;



    [ 06-13-2002: Message edited by: moki ]</p>
  • Reply 174 of 239
    thttht Posts: 5,605member
    <strong>Originally posted by Programmer:

    Well here are the "facts" that I'm aware of (plus one supposition), and I think they explain what everybody is saying even though the end result still isn't as happy as a G5 w/ on-chip memory controller....</strong>



    Um, I used to think, 2 or 3 years ago, that on-chip memory controllers would be cool, but that was when I didn't understand the economics very well. Processor performance will always be way beyond memory performance (with semiconductors). So, any memory technology in the near future will never be able to provide the bandwidth for a modern CPU, and I think the magic should be in the cache design, but I digress.



    The economics is that I don't think there is any need for anything more than a dual processor machine in the consumer space for one reason, Moore's Law. Next gen fab tech doubles the number of transistors that a consumer CPU can have thereby eliminating the need for anything more for dual processor machines, if that. In addition, I wonder at the efficacy of dual processors when compared to CMP and or SMT designs.



    Since that is the case imo, a shared memory architecture should be able to compete with any on-die memory controller, and I don't think it is worth the effort to design a NUMA architecture for a market that really doesn't need it and is more expensive then a shared system to boot.



    So a hypothetical PPC with monster backside cache (16 to 128 MByte at &gt;8 GByte/s bandwidth) and a RapidIO/Hypertransport bus is fine with me.



    <strong>Moto's head of PPC development has said that MPX will not be significantly changed because the embedded customers are very happy with it and compatibility doesn't want to become an issue. A speed bump to 166 MHz is possible at some unspecified point in time. This means no DDR MPX, and maximum of 1.3 GB/sec.</strong>



    I can't for the life of me think why DDR signalling for a MPX bus would be a significant change??? But I do think that economically and politically, Motorola seems to be getting out of the system ASIC business, is simply dragging its feet on DDR MPX, and is waiting for CPUs with on-die memory controllers to ship.



    <strong>Current PowerMacs achieve ~800 MB/sec in practice under very optimized circumstances. This is about 80% efficiency, which is remarkable from SDRAM who's theoretical peak is ~1 GB/sec. Usually it is more like 700 MB/sec or so.</strong>



    If this is true, the MPX bus already provides the memory bandwidth seen in x86 PC2100 DDR SDRAM systems. If it's true. Probably for random I/O, but for streaming reads, who knows.
  • Reply 176 of 239
    thttht Posts: 5,605member
    re: Apple PI, pipelining instructions.



    Hmm... new memory instructions? Like better prefetch, multiple pipelined prefetch? Concurrent or simultaneous memory instructions? Real-time?



    Speculation is fun.
  • Reply 177 of 239
    frawgzfrawgz Posts: 547member
    [quote]Originally posted by moki:

    <strong>



    Sure, until the 2.4ghz Xeon and the 2.5ghz P4, the POWER4 was the undisputed champ compared to the 2.2ghz P4 (the next closest contendor).



    Take a look at the floating point performance, though -- the POWER4 is still the champ by a good margin:



    <a href="http://www.ideasinternational.com/benchmark/spec/specfp_s2000.html"; target="_blank">http://www.ideasinternational.com/benchmark/spec/specfp_s2000.html</a>;



    That's pretty impressive for a chip that is almost half the clockspeed -- imagine how it will do at 2ghz or so, using a .13 micron process (or even a .9 micron process and yet higher clockspeeds).



    The POWER4 has legs, folks.



    [ 06-13-2002: Message edited by: moki ]</strong><hr></blockquote>



    Hey, that's good news. I was about to have an aneurysm. But we're only talking about chips now, aren't we? Still, it's important that Apple get its act together in that arena soon, as others have stated.



    I'm sure this is a question whose answer will probably be obfuscated by other factors, but as great as the POWER4 may be, how important is it to us now? I don't want to get my hopes up for some POWER implementation in a PowerMac some time in the future. Moki, you brought it up to show that the PowerPC has legs, right? Or is there another reason you brought it up.. It seems we might be getting carried away with this, that's all.
  • Reply 178 of 239
    mokimoki Posts: 551member
    [quote]Originally posted by frawgz:

    <strong>I'm sure this is a question whose answer will probably be obfuscated by other factors, but as great as the POWER4 may be, how important is it to us now? I don't want to get my hopes up for some POWER implementation in a PowerMac some time in the future. Moki, you brought it up to show that the PowerPC has legs, right? Or is there another reason you brought it up.. It seems we might be getting carried away with this, that's all.</strong><hr></blockquote>



    I believe the next major chip Apple will use in its computers will not be from MOT -- and IBM is at the top of the list in terms of who the new dancing partner will be.



    See you in a year.
  • Reply 179 of 239
    iridiumiridium Posts: 13member
    Hi,

    Let me come back to the posted SPEC Data for the POWER4 vs. the P4.



    While a P4 may generate higher results in SPEC, you have to know where they come from.



    Not only the POWER 4gains better results in the FP test, but (a board member already stated here) ...

    the SPEC Test doesn't make use of the processing unit

    of the POWER4.



    Therefore IMHO you have to consider the POWER4 to be much much better, IF the CPU is approached consequently.



    You see that kind of discussion very much in the sgi newsgroups, too ... :-) ...



    As far as the results of the recent real world benchmarks go ... (p4/Athlon smoking a G4 in AfterFX)..



    Please keep in mind, that AfterFX is not really well programmed in a way a MP G4 could benefit.



    As far as i have been informed .... AfterFX just uses one CPU.



    My proposition for a real world test would be ...



    Take a Clip.

    Commence some editing on Premiere/mac.

    Do the same with Final Cut.

    Do the same with Premiere/pc.



    Compare...



    Voila ... This could be surprising ...



    Cheers,

    P.S.:



    Sorry, my English is quite rusty. I am not used to it anymore. However, please appreciate the effort ...
  • Reply 180 of 239
    mokimoki Posts: 551member
    [quote]Originally posted by THT:



    <strong>Current PowerMacs achieve ~800 MB/sec in practice under very optimized circumstances. This is about 80% efficiency, which is remarkable from SDRAM who's theoretical peak is ~1 GB/sec. Usually it is more like 700 MB/sec or so.</strong>



    If this is true, the MPX bus already provides the memory bandwidth seen in x86 PC2100 DDR SDRAM systems. If it's true. Probably for random I/O, but for streaming reads, who knows.<hr></blockquote>



    From MOT's whitepaper on the G4:



    <a href="http://e-www.motorola.com/brdata/PDFDB/docs/G4WP.pdf"; target="_blank">http://e-www.motorola.com/brdata/PDFDB/docs/G4WP.pdf</a>;



    [code]

    Comparison of Bus Bandwidths in (Mbytes/sec.)



    Device Bus Freq Peak Maximum Sustained

    MPC750 100MHz 800 640 246

    MPC74xx 100MHz 800 640 640

    MPC74xx 133MHz 1064 851 851

    </pre><hr></blockquote>
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