the 620 was actually a joint development of IBM and MOTO and was by far the fastest of all G2 chips.
A 133MHz model performed at 390 MIPS and had 7mio transistors, while the 604 only had 300 MIPS and 3.6mio transistors and only hit 133 half a year later.
Building a G3 or G4 off the 620 design would have resulted in a killer CPU, alhtough also expensive and power-hungry.
Starting with the 603ev as base CPU was probably a fairly Intellish decision: scalable and dirt cheap.
Too bad it was even slower than a Pentium 1 at the same clockspeed.
The PPC family has had a lot of awkward development, it's about time to make a new branch in that tree and give us something really nice.
<strong>The 604e did have a L2 cache on the mainboard (256 or 512k). Problem was, that this cache only ran with Bus-speed (which was 50MHz max.). Therefore it was slower than the L2-Cache of the G3. There was one version of the 604e which used backside-cache. This was used only in the very last revision of the 9600 ( <a href="http://docs.info.apple.com/article.html?artnum=112424"; target="_blank">http://docs.info.apple.com/article.html?artnum=112424</a>; ).
</strong><hr></blockquote>
Did you even read what I wrote? There was no version of the 604e with a backside cache. There was no 604e processor with any L2 cache. The link you posted shows the L2 cache on either the motherboard or the daughter card and it sits on the frontside bus. In order for a processor to have a "backside cache" it needs an on-chip L2 cache controller and an additiona set of data/address lines going into the processor. The 60x series had no such thing, and this was the big speed difference in the G3. You are confusing what is part of the overall system and what is part of the CPU.
[quote]<strong>
The 604e was faster than the g3 because it had an integrated FPU. Especially the last revision (300 and 350 MHz) with 1 MB backside-cache was much faster than the G3 (and much more expensive). The G3 tried to compensate the missing FPU by using faster L2-cache. This worked well in general use, but FPU-intensive tasks are much slower. The G3 felt(!) a little more responsive than the 604e, but the 604e was overall the faster CPU.
</strong><hr></blockquote>
The G3 has an integrated FPU -- all PowerPCs used by Apple do. The 604 just had a faster FPU, although the major difference was only evident in double precision floating point calculations. The 604e had a variety of internal details that were superiour to the G3 (more execution units, 4 way superscalar, larger TLB, more rename registers, full SMP support with MESI, etc) which is why it was in some ways faster. As the clock rates increased, however, the G3's backside L2 cache performance had a much bigger impact on performance and eclipsed the 604's better architecture. Most of the 604's superiour features have been incorporated into the G4 series over time, and the G4 also has the backside L2 cache (the latest G4s have an on-chip L2 and some have a backside L3 as well).
Note that there have been versions of the G3 and G4 without the backside cache, and they are significantly slower. Apple hasn't used them, except perhaps in some notebooks (??).
The 604 (16/16KB I/D L1 cache) and 604e (32/32KB I/D L1 cache) has no support for backside cache. That's no support for backside cache. Backside cache is a cache that has a dedicated bus to the CPU.
The 604 machines had an L2 cache on its processor bus running at 50 MHz. The 604e machines had an L2 cache on a clock doubled processor bus. From CPU to L2 cache it was 100 MHz, from the clock doubling chip to the core logic chip (which bridged the main memory bus) it was 50 MHz.
The 604e's advantage in FPU was that it can do double precision ops with a latency of 3 cycles while the 750 FPU would do them with a latency of 4 cycles. Single precision, divides, higher order functions were the same or very very close. Since it was more memory starved compared to the 750 with backside cache, it's advantage in FPU wasn't that great.
The main thing about the 604e was it was a 4-way dispatch 4-way completion CPU. It was able to handle more instructions at the same time. It takes some time for compilers and apps to be optimized for this, on the order of 3 or 4 years, and it would have been better to use the 604 as the base for improvements instead of the 603e, since wider CPUs are the way it would have ended up anyways.
<strong>Moto still sells 400Mhz 604ev processors. If they moved it to 180nm and 130nm it should scale higher than the 750. The 750FX also has a 5 stage pipeline and it's a 180nm chip that runs at 700-800MHz. A 130nm 604 would run at least 1GHz.</strong><hr></blockquote>
You are correct that the 750fx has a 5 stage instruction pipeline. However, it is manufactured on the .13u process, not a .18u process as you suggest. Likewise, the basis of your conclusion regarding projected 604 speed is without merit.
I thought the eMac and iMac and the base powermac (as well as the old TiBooks) all lacked backside (L3 cache). I don't know off the top off my head about any G4s without L2 however
DO you think they will bring back a Double Precision floating point unit? I know it seems to be missed in Scientific Applications (Apple's ACG spends a bit of effort explaining how to compensate for the lack). Are their benefits to double precision floating point math for general apps?
old i know, but dammit anything is better than nothing ..
[quote]Motorola taped out the PowerPC 8500 - aka the G5 - last week and is set to go into volume production real soon now at speeds of up to 1.6GHz - a higher clock speed than AMD's latest-generation, 'Palomino' Athlon is expected to ship at - The Register has learned.
So claim sources said to be close to Apple, at any rate. The new CPU will be offered at 800MHz, 1GHz, 1.2GHz, 1.4GHz and 1.6GHz, and while the first two are nominally aimed at the embedded space - the others are aimed straight at the desktop, we hear - we can see Apple using them as to transition over from the top end G4, the PowerPC 7450.<hr></blockquote>
<strong>DO you think they will bring back a Double Precision floating point unit? I know it seems to be missed in Scientific Applications (Apple's ACG spends a bit of effort explaining how to compensate for the lack). Are their benefits to double precision floating point math for general apps?</strong><hr></blockquote>
The G4's FPU is equivalent (or better) than the 604's. The compensation article I believe you are refering to is for using the AltiVec unit, which only supports integer and single precision floating point. The could add a 2x double type to the AltiVec unit, but I doubt they will -- adding a second FPU would be more effective.
"Now, they have the bus, they may find that G5 drains too much power."
huh? what bus? DDR166->333 bus that's expected on UMA2.0 expected in 2 weeks? A little after MWSF2002, i heard rumors of a 500MHz Rapid-IO bus from an "insider", but I'm not holding my breath on that...
As for G5...depending on what you/Apple qualify as G5. The original G4 was just G3+vector processor, and wasn't a "real G4" 'til the 7440/50 chips came out with complete re-design. I'm sure a lot of you have heard rumors of a 10-stage-pipelined Gx chip due for release...maybe that's the G5? who knows...Granted a 4 stage-pipe wasn't realistic in terms of CPU clock, but at this rate, what's next? a jump to 20 stage-pipeline to match that of the P4 so it can compete in clock speed? (10-stage-pipe is what the P3 used, and only got to what? 1.3GHz? I'm guessing G4+ won't fare too much better in raw CPU cycle. 13-stage-piped Athlon is more/less stuck at 1.7GHz, with their latest offering only like 1% faster than the previous Top-of-line)
Will the playing field level out in the next year?
Can Intel keep pushing the mhz to 4 gig and beyond?
When/if the Itanium goes mainstream the G5 will be there to meet it? Or will the be P4 keep scaling?
Yeah, the Athlon has become stuck...but Sledgehammer is around the corner. Will it be high mhz or merely get a 'performance rating' and be stuck at present mhz. I heard AMD are having problems with it?
How much more can you add to a G4 without changing its name? G4 was released originally with only 4 pipelines as the G3, with half speed L2 cache and of course Altivec. FSB and System Bus was originally at 100 MHZ. Since the introduction of 7450, Motorola has redesigned the G4 with 3 more pipelines, increasing its clock frequency. FSB and System bus also improves to 133 MHZ. L2 cache now runs at 1:1 ratio to processor speed. The progress goes further to implement SOI to HIPERMOS 6 to allow the enhanced version of 7455 to deliver higher clock frequency with L3 cache. According to Motorola roadmap, all major criteria of 74XX series (G4) platform have been fully implemented with clock frequency achieving 1GHZ, Altivec along with SOI. Now, I think its time to introduce new series of desktop computing chip for Apple. With the addition of HiPERMOS 7, the roadmap points out that the fifth generation of PPC will be an all-new architecture. New bus topology, new pipelines as well as new .13 process will be used. Rumors have it that G5 will be delay until 2003 and Motorola will continue to stretch the legs of G4. However, even 7455 with L3 cache and higher frequency doesn’t spark pro sales, I don’t see any new G4 improvements will. The market is expecting a new architecture and more significant improvements. So if G4 is to get a improve DDR 2700 FSB, even such improvement will be consider a joke versus Intel bus architecture. And if G4 gets a rapid IO feature from the G5, it will steal one of the major feature of G5. And in terms of MHZ, higher clock frequency, it could easily be obtained by adding pipes, but by doing so will also steal another major feature of G5. And although, G4 has been rumor to have more MHZ upside, I do not predict more than 300 MHZ, because of power requirement will require a lot more cooling even with SOI. So the only logical way of looking at it is, the G5 will be introduced at NY and it will have RAPID IO, new buses, new architecture, new pipes and other goodies.
I agree. I think it would be a slip if they can't the G5 out (as well as mobos, etc)this N.Y. S.F by the latest. Not the end of the world but it's time.
One point I would like to make to all those who are concerned with the PPC architecture versus Intel AMD. It is becoming more apparent that the conservative road the PPC is taking (while more conservative then I would like) is really the future of computing in that the processor balances heat and power.
It looks to me that both Intel and AMD are pushing the limits of heat and efficiency in the wrong direction and are flying high and fast towards the sun.
Then of course x86 wasn't suppose to scale so nicely and compete performance wise with RISC..
<strong>I agree. I think it would be a slip if they can't the G5 out (as well as mobos, etc)this N.Y. S.F by the latest. Not the end of the world but it's time.
One point I would like to make to all those who are concerned with the PPC architecture versus Intel AMD. It is becoming more apparent that the conservative road the PPC is taking (while more conservative then I would like) is really the future of computing in that the processor balances heat and power.
It looks to me that both Intel and AMD are pushing the limits of heat and efficiency in the wrong direction and are flying high and fast towards the sun.
Then of course x86 wasn't suppose to scale so nicely and compete performance wise with RISC..
x86 cheated! They only got to 2.53GHz because they started super-pipelining. Even at .18-micron, the 7-stage G4 can reach 1GHz+.
Impressive, given the fact that the 10-stage .18-micron P3 can't run above 1GHz. Maybe there is some truth to the RISC myth?
Then again, it may just be because the G4 has a better transistor layout. Wait, a better transistor layout because it's RISC, or just a different chip?
<strong>One point I would like to make to all those who are concerned with the PPC architecture versus Intel AMD. It is becoming more apparent that the conservative road the PPC is taking (while more conservative then I would like) is really the future of computing in that the processor balances heat and power.
It looks to me that both Intel and AMD are pushing the limits of heat and efficiency in the wrong direction and are flying high and fast towards the sun.
Thank you for providing an article that proves my point! Quoted from the article in question:
[quote]
The 604e (and 603e) lacks connectors for a backside cache, but systems designers can nonetheless increase cache speed through an in-line cache, which, like backside cache, uses a high-speed connector to the CPU.
Unlike with backside cache, the speed of in-line cache is limited by its connection to the main system bus. In-line cache technology currently can only double the cache-bus speed, bringing it to 100MHz from the 50MHz maximum system-bus speed for most Macs. Thus, for example, with a 300MHz PowerPC 604e, the top bus speed of in-line cache is 100MHz, which makes the CPU wait longer for cache data than a 300MHz PowerPC 750 would with a 300MHz or even 150MHz backside cache.
<hr></blockquote>
As you can see the 604e provides no connector or direct support for an L2 cache -- it is a feature of the motherboard not the processor. You are confusing the system with the processor. If you buy a 604e processor from Motorola or IBM you will get no built in L2 cache support.
Comments
A 133MHz model performed at 390 MIPS and had 7mio transistors, while the 604 only had 300 MIPS and 3.6mio transistors and only hit 133 half a year later.
Building a G3 or G4 off the 620 design would have resulted in a killer CPU, alhtough also expensive and power-hungry.
Starting with the 603ev as base CPU was probably a fairly Intellish decision: scalable and dirt cheap.
Too bad it was even slower than a Pentium 1 at the same clockspeed.
The PPC family has had a lot of awkward development, it's about time to make a new branch in that tree and give us something really nice.
G-news
<strong>The 604e did have a L2 cache on the mainboard (256 or 512k). Problem was, that this cache only ran with Bus-speed (which was 50MHz max.). Therefore it was slower than the L2-Cache of the G3. There was one version of the 604e which used backside-cache. This was used only in the very last revision of the 9600 ( <a href="http://docs.info.apple.com/article.html?artnum=112424"; target="_blank">http://docs.info.apple.com/article.html?artnum=112424</a>; ).
</strong><hr></blockquote>
Did you even read what I wrote? There was no version of the 604e with a backside cache. There was no 604e processor with any L2 cache. The link you posted shows the L2 cache on either the motherboard or the daughter card and it sits on the frontside bus. In order for a processor to have a "backside cache" it needs an on-chip L2 cache controller and an additiona set of data/address lines going into the processor. The 60x series had no such thing, and this was the big speed difference in the G3. You are confusing what is part of the overall system and what is part of the CPU.
[quote]<strong>
The 604e was faster than the g3 because it had an integrated FPU. Especially the last revision (300 and 350 MHz) with 1 MB backside-cache was much faster than the G3 (and much more expensive). The G3 tried to compensate the missing FPU by using faster L2-cache. This worked well in general use, but FPU-intensive tasks are much slower. The G3 felt(!) a little more responsive than the 604e, but the 604e was overall the faster CPU.
</strong><hr></blockquote>
The G3 has an integrated FPU -- all PowerPCs used by Apple do. The 604 just had a faster FPU, although the major difference was only evident in double precision floating point calculations. The 604e had a variety of internal details that were superiour to the G3 (more execution units, 4 way superscalar, larger TLB, more rename registers, full SMP support with MESI, etc) which is why it was in some ways faster. As the clock rates increased, however, the G3's backside L2 cache performance had a much bigger impact on performance and eclipsed the 604's better architecture. Most of the 604's superiour features have been incorporated into the G4 series over time, and the G4 also has the backside L2 cache (the latest G4s have an on-chip L2 and some have a backside L3 as well).
Note that there have been versions of the G3 and G4 without the backside cache, and they are significantly slower. Apple hasn't used them, except perhaps in some notebooks (??).
The 604 machines had an L2 cache on its processor bus running at 50 MHz. The 604e machines had an L2 cache on a clock doubled processor bus. From CPU to L2 cache it was 100 MHz, from the clock doubling chip to the core logic chip (which bridged the main memory bus) it was 50 MHz.
The 604e's advantage in FPU was that it can do double precision ops with a latency of 3 cycles while the 750 FPU would do them with a latency of 4 cycles. Single precision, divides, higher order functions were the same or very very close. Since it was more memory starved compared to the 750 with backside cache, it's advantage in FPU wasn't that great.
The main thing about the 604e was it was a 4-way dispatch 4-way completion CPU. It was able to handle more instructions at the same time. It takes some time for compilers and apps to be optimized for this, on the order of 3 or 4 years, and it would have been better to use the 604 as the base for improvements instead of the 603e, since wider CPUs are the way it would have ended up anyways.
<strong>Moto still sells 400Mhz 604ev processors. If they moved it to 180nm and 130nm it should scale higher than the 750. The 750FX also has a 5 stage pipeline and it's a 180nm chip that runs at 700-800MHz. A 130nm 604 would run at least 1GHz.</strong><hr></blockquote>
<a href="http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/2FF4861D6755A6CA87256BB1006B1DE6/$file/PPC750FX_PB.PDF"; target="_blank">http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/2FF4861D6755A6CA87256BB1006B1DE6/$file/PPC750FX_PB.PDF</a>;
You are correct that the 750fx has a 5 stage instruction pipeline. However, it is manufactured on the .13u process, not a .18u process as you suggest. Likewise, the basis of your conclusion regarding projected 604 speed is without merit.
Steve
DO you think they will bring back a Double Precision floating point unit? I know it seems to be missed in Scientific Applications (Apple's ACG spends a bit of effort explaining how to compensate for the lack). Are their benefits to double precision floating point math for general apps?
Unfortunately, it's taken this way off topic. It might be wise to re-rail this thread before it gets moved to "past hardware".
could be interesting ... i think
old i know, but dammit anything is better than nothing ..
[quote]Motorola taped out the PowerPC 8500 - aka the G5 - last week and is set to go into volume production real soon now at speeds of up to 1.6GHz - a higher clock speed than AMD's latest-generation, 'Palomino' Athlon is expected to ship at - The Register has learned.
So claim sources said to be close to Apple, at any rate. The new CPU will be offered at 800MHz, 1GHz, 1.2GHz, 1.4GHz and 1.6GHz, and while the first two are nominally aimed at the embedded space - the others are aimed straight at the desktop, we hear - we can see Apple using them as to transition over from the top end G4, the PowerPC 7450.<hr></blockquote>
<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
Or...is the Register off beam on this? They seem to a reputable site to me. But rumours are ultimately that.
Given Motorola's product ramp...we may see the G5 anytime from Macworld New York this year until same time next year!
Instinct tells me that Apple and Moto will eek one more revision out of the G4 before we get the G5. Sad but true.
My realistic side says Macworld San Fran 2003 for the G5. That's late already in my view.
But I'd take New York this year!!! :eek:
Lemon Bon Bon
<strong>DO you think they will bring back a Double Precision floating point unit? I know it seems to be missed in Scientific Applications (Apple's ACG spends a bit of effort explaining how to compensate for the lack). Are their benefits to double precision floating point math for general apps?</strong><hr></blockquote>
The G4's FPU is equivalent (or better) than the 604's. The compensation article I believe you are refering to is for using the AltiVec unit, which only supports integer and single precision floating point. The could add a 2x double type to the AltiVec unit, but I doubt they will -- adding a second FPU would be more effective.
huh? what bus? DDR166->333 bus that's expected on UMA2.0 expected in 2 weeks? A little after MWSF2002, i heard rumors of a 500MHz Rapid-IO bus from an "insider", but I'm not holding my breath on that...
As for G5...depending on what you/Apple qualify as G5. The original G4 was just G3+vector processor, and wasn't a "real G4" 'til the 7440/50 chips came out with complete re-design. I'm sure a lot of you have heard rumors of a 10-stage-pipelined Gx chip due for release...maybe that's the G5? who knows...Granted a 4 stage-pipe wasn't realistic in terms of CPU clock, but at this rate, what's next? a jump to 20 stage-pipeline to match that of the P4 so it can compete in clock speed? (10-stage-pipe is what the P3 used, and only got to what? 1.3GHz? I'm guessing G4+ won't fare too much better in raw CPU cycle. 13-stage-piped Athlon is more/less stuck at 1.7GHz, with their latest offering only like 1% faster than the previous Top-of-line)
I like what you said...
Kernals of future hope for Apple in what you say?
Will the playing field level out in the next year?
Can Intel keep pushing the mhz to 4 gig and beyond?
When/if the Itanium goes mainstream the G5 will be there to meet it? Or will the be P4 keep scaling?
Yeah, the Athlon has become stuck...but Sledgehammer is around the corner. Will it be high mhz or merely get a 'performance rating' and be stuck at present mhz. I heard AMD are having problems with it?
Lemon Bon Bon
One point I would like to make to all those who are concerned with the PPC architecture versus Intel AMD. It is becoming more apparent that the conservative road the PPC is taking (while more conservative then I would like) is really the future of computing in that the processor balances heat and power.
It looks to me that both Intel and AMD are pushing the limits of heat and efficiency in the wrong direction and are flying high and fast towards the sun.
Then of course x86 wasn't suppose to scale so nicely and compete performance wise with RISC..
[ 06-26-2002: Message edited by: tink ]</p>
<strong>I agree. I think it would be a slip if they can't the G5 out (as well as mobos, etc)this N.Y. S.F by the latest. Not the end of the world but it's time.
One point I would like to make to all those who are concerned with the PPC architecture versus Intel AMD. It is becoming more apparent that the conservative road the PPC is taking (while more conservative then I would like) is really the future of computing in that the processor balances heat and power.
It looks to me that both Intel and AMD are pushing the limits of heat and efficiency in the wrong direction and are flying high and fast towards the sun.
Then of course x86 wasn't suppose to scale so nicely and compete performance wise with RISC..
[ 06-26-2002: Message edited by: tink ]</strong><hr></blockquote>
x86 cheated! They only got to 2.53GHz because they started super-pipelining. Even at .18-micron, the 7-stage G4 can reach 1GHz+.
Impressive, given the fact that the 10-stage .18-micron P3 can't run above 1GHz. Maybe there is some truth to the RISC myth?
Then again, it may just be because the G4 has a better transistor layout. Wait, a better transistor layout because it's RISC, or just a different chip?
<strong>
There was no version of the 604e with a backside cache. (??).</strong><hr></blockquote>
You are right! It had an Inline-Cache!
[quote]Originally posted by Programmer:
<strong>
There was no 604e processor with any L2 cache.</strong><hr></blockquote>
You are wrong!
<a href="http://www.macworld.com/1997/10/features/3912.html"; target="_blank">http://www.macworld.com/1997/10/features/3912.html</a>;
<strong>One point I would like to make to all those who are concerned with the PPC architecture versus Intel AMD. It is becoming more apparent that the conservative road the PPC is taking (while more conservative then I would like) is really the future of computing in that the processor balances heat and power.
It looks to me that both Intel and AMD are pushing the limits of heat and efficiency in the wrong direction and are flying high and fast towards the sun.
</strong><hr></blockquote>
Might find this <a href="http://www.nytimes.com/2002/06/25/science/physical/25COMP.html?pagewanted=1&8isc"; target="_blank">NY Times</a> (free registration req) article interesting
Too bad it was even slower than a Pentium 1 at the same clockspeed.<hr></blockquote>
The 603 was slow, but the 603e (and 603ev) corrected these problems (mainly by a more generous amount of l1 cache).
<strong>You are wrong!
<a href="http://www.macworld.com/1997/10/features/3912.html"; target="_blank">http://www.macworld.com/1997/10/features/3912.html</a></strong><hr></blockquote>;
Thank you for providing an article that proves my point! Quoted from the article in question:
[quote]
The 604e (and 603e) lacks connectors for a backside cache, but systems designers can nonetheless increase cache speed through an in-line cache, which, like backside cache, uses a high-speed connector to the CPU.
Unlike with backside cache, the speed of in-line cache is limited by its connection to the main system bus. In-line cache technology currently can only double the cache-bus speed, bringing it to 100MHz from the 50MHz maximum system-bus speed for most Macs. Thus, for example, with a 300MHz PowerPC 604e, the top bus speed of in-line cache is 100MHz, which makes the CPU wait longer for cache data than a 300MHz PowerPC 750 would with a 300MHz or even 150MHz backside cache.
<hr></blockquote>
As you can see the 604e provides no connector or direct support for an L2 cache -- it is a feature of the motherboard not the processor. You are confusing the system with the processor. If you buy a 604e processor from Motorola or IBM you will get no built in L2 cache support.
Got it yet?
[ 06-26-2002: Message edited by: Programmer ]</p>