Interesting DP Tidbit From Developer Article
This isn't a rumor but it is perhaps a sign of things to come, and I thought it was worth posting since things are slow right now anyway. In Apple's new G5 optimization developer article, we find the following statement:
Dual-processor Power Mac G5 models include separate frontside buses to each G5 processor; this gives them an extra speed advantage over dual-processor Intel computers, which force both processors to share a single bus.
Article Link
Now I'm probably reading too much into this, but note the plural case, DP "models include. . ." There's only one DP model right now. I realize it's basically nothing, but it caught my eye.
Dual-processor Power Mac G5 models include separate frontside buses to each G5 processor; this gives them an extra speed advantage over dual-processor Intel computers, which force both processors to share a single bus.
Article Link
Now I'm probably reading too much into this, but note the plural case, DP "models include. . ." There's only one DP model right now. I realize it's basically nothing, but it caught my eye.
Comments
From now on all dual-processor Power Mac G5 models will include separate frontside buses to each G5 processor.
Multi core chips seem one way to do this, but perhaps it would be possible to do a G4 type arrangement with two CPU's on one card if it allows Apple to make a smaller cheaper Mobo for dual machines in the lower end. The bandwidth, even in such a config, would still be very high.
Think about it. Each G5 is still only getting half of the theoretical 7.2Gbps bandwidth. The way to maximize performance would be two memory controllers. That way each processor would have the ful 6.4Gbps memory throughput.
Originally posted by hmurchison
Who cares if the Busses are seperate you still have a logjam at the Memory Controller.
It's not a perfect solution to have two memory controllers, like in a NUMA architecture, because then each processor has a serious time hit accessing the memory that's owned by the other processor, and managing that memory can be a problem.
-- Mark