Geek.com: G5+
<a href="http://www.geek.com/procspec/apple/g5+.htm"; target="_blank">http://www.geek.com/procspec/apple/g5+.htm</a>;
Another G5 chip coming our way? I'm still waiting for the first one.
Another G5 chip coming our way? I'm still waiting for the first one.
Comments
Can we have the first one please?
Lemon Bon Bon <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
Sounds like it would be good to me. But I'm not holding my breath for a G5 of anykind. I don't think we'll see one in 2002 from Apple. <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
The name of the chip is decided by the manufacturer, not apple. Motorola will make a G5. Cisco has already signed a contract to buy a bunch. Apple just buys them, they don't make them, design them, name them, release them soon, anything, they just BUY them.
This is for the couple of people who said that Apple should not put a L3 cache on the chip.
<strong>The name of the chip is decided by the manufacturer, not apple. Motorola will make a G5. Cisco has already signed a contract to buy a bunch. Apple just buys them, they don't make them, design them, name them, release them soon, anything, they just BUY them.</strong><hr></blockquote>
Ummm, no.
Apple gives it the name G3, G4, G5, Getc...
Apple has input to the design (no matter how limited it is, it does exist). Apple is part of the joint venture between themselves, IBM and Motorola (usually refered to as AIM, imagine that).
Go to Motorola's site, you'll see the names 750, 7400 and such refering to the chips placed into our Powermacs. Apple coins the numbering for the G-series.
I understand how DDR works with data being transferred on both the rising and falling edge of the pulse. I don't understand what 133MHz*4 means.
<strong>Any hardware people out there who can explain how the bus speed of 533MHz (133MHz*4) works?
I understand how DDR works with data being transferred on both the rising and falling edge of the pulse. I don't understand what 133MHz*4 means.</strong><hr></blockquote>
Basically, it means that the system bus runs at 133mhz, but there are two DDR pathways from the processor to RAM, and since DDR can access memory twice per bus clock cycle, you get 133mhz * 2 (DDR) * 2 (memory pathways) = 133mhz * 4, or, a theoretical 533mhz memory bus.
Of course, the numbers don't work out quite that nicely in real-world applications, but you get the idea.
Best
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Ed M.
The problem is that it is really hard to make a signal go at 533 mhz, as you get faster and faster you get all sorts of nasty problems creeping in on the circuit board. These are not issues for the chips, but the design and manufacture of the board that the chips go on.
Someone noticed that instead of doubling the speed of the clock you could use the rising and falling transitions that already existed to achieve the same result ( hence DDR ). It wasnt done before because at slower speeds it was easier to increase the speed of the clock.
QDR uses two clock signals, 90 degrees [?] out of phase with each other.
Level 3 cache:
All cache is a trade off. Larger caches are slower to access. If you look at the P4, it has a very small L1 cache, but it is very fast. While the Athlon has a larger slower L1. This gives them different memory access profiles.
Deciding how to structure caches requires extensive analysis of code patterns, and some good guesses about future algorithms.
At any rate, it is better to have a smaller L2, that keeps the processor going faster most of the time ( till it misses ), than a larger cache that misses less often, but is always slower. But, the precise point where that happens I couldnt tell you, but it is a balance of existing code requirements ( Moto are very orientated toward the embedded market ), future code requirements, and cost.
Barto
<strong>Don't forget the <a href="http://www.geek.com/procspec/apple/g6.htm"; target="_blank">G6</a> and <a href="http://www.geek.com/procspec/apple/g7.htm"; target="_blank">G7</a>.
Geek.com is expecting the G7 by "late 2004." Assuming the G5 comes out at MWSF (a very big assumption unfortunately), this site believes AIM will jump two whole processor generations in one year. . . I'd certainly like to know what those individuals are smoking, RDF-laced something or other.
<a href="http://www.geek.com/procspec/apple/g5.htm"; target="_blank">http://www.geek.com/procspec/apple/g5.htm</a>;
But it was funny, because they posted detailed specs of this G5 that Moto wasn't going to make!
However, the G5+ could easily be the second version of the G5, since the first G5, the 8540, was made for the embedded market and doesn't even use altivec. Maybe this G5+ is an enhanced 8540 with altivec and some other additions to make it work better for a desktop computer?
I doubt it, but it's fun to speculate, although I have more faith in spymac than I do in geek.com's BS.
<strong>How QDR works:
At any rate, it is better to have a smaller L2, that keeps the processor going faster most of the time ( till it misses ), than a larger cache that misses less often, but is always slower. But, the precise point where that happens I couldnt tell you, but it is a balance of existing code requirements ( Moto are very orientated toward the embedded market ), future code requirements, and cost.</strong><hr></blockquote>
Sorry but i don't understand your point ,if it was true why the new P4 has a larger cache than the previous (and is more performant at equal mhz) and why the Xeon have the largest L2 cache.
I think that you make some confusion of the subject.
There is three sort of L2 cache,
- L2 cache on the mobo, like it appears in the PPC 604 for example, very slow
- L2 cache on the CPU card like the G3 750 first generation and the G4 7400 or 7410
- L2 cache on die (on the chip) like the P4, Modern AThlon, Xeon, 7450, 7455, G3 740 fxe , 750 fx.
This lattest of these cache is the fastest, generally it's only 256 KB of sise compared to 1 MB from the others versions (and if you compare the first version to the lattest version what you say is true), but if you compare the size of cache of the lattest version the more is the better. In the PPC family the best L2 cache is the Sahara chip : 512 KB L2 cache 256 bit full speed on die, the slowest is the 750 fxe, 256 KB L2 cache 64 bit on die.
But if you can design a 256 bit on die L2 cache of 2 MB it will rock.
<strong>But if you can design a 256 bit on die L2 cache of 2 MB it will rock.</strong><hr></blockquote>
yeah, at the cost of millions of transistors and making the chip much more expensive than it already is! If you look at the part price on the G4+ chips, they are more expensive than the top-of-the-line P4s!
I think instead of a 2MB L2 cache, if they improve branch-prediction, that'll make more of a difference, especially since the Gx processors are increasing the number of stages of their pipeline...If the Gx's BPU can match that of the P4, then 2MB of L2 won't make that much difference compared to 1MB of L2...