yeah, at the cost of millions of transistors and making the chip much more expensive than it already is! If you look at the part price on the G4+ chips, they are more expensive than the top-of-the-line P4s!
I think instead of a 2MB L2 cache, if they improve branch-prediction, that'll make more of a difference, especially since the Gx processors are increasing the number of stages of their pipeline...If the Gx's BPU can match that of the P4, then 2MB of L2 won't make that much difference compared to 1MB of L2...</strong><hr></blockquote>
You are right, (for the price of the G4 : i don't know) , i was answering to a guy here, who said that larger L2 cache was less performant than small ones, and to another guy saying that there will be 2 mB L3 cache on the chip with 512 K L2 cache (my point was that : no need of this L3 cache on the chip, better have directly a 2 MB L2 cache).
Comments
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yeah, at the cost of millions of transistors and making the chip much more expensive than it already is! If you look at the part price on the G4+ chips, they are more expensive than the top-of-the-line P4s!
I think instead of a 2MB L2 cache, if they improve branch-prediction, that'll make more of a difference, especially since the Gx processors are increasing the number of stages of their pipeline...If the Gx's BPU can match that of the P4, then 2MB of L2 won't make that much difference compared to 1MB of L2...</strong><hr></blockquote>
You are right, (for the price of the G4 : i don't know) , i was answering to a guy here, who said that larger L2 cache was less performant than small ones, and to another guy saying that there will be 2 mB L3 cache on the chip with 512 K L2 cache (my point was that : no need of this L3 cache on the chip, better have directly a 2 MB L2 cache).
[ 07-09-2002: Message edited by: sc_markt ]</p>