nForce 2 announced
and nvidia joins HyperTransport group. hmmm.....
<a href="http://maccentral.macworld.com/news/0207/15.hypertransport.php"; target="_blank">http://maccentral.macworld.com/news/0207/15.hypertransport.php</a>;
<a href="http://maccentral.macworld.com/news/0207/15.hypertransport.php"; target="_blank">http://maccentral.macworld.com/news/0207/15.hypertransport.php</a>;
Comments
Jet
<a href="http://www.e-insite.net/ednmag/index.asp?layout=article&articleId=CA223201"; target="_blank">http://www.e-insite.net/ednmag/index.asp?layout=article&articleId=CA223201</a>;
<strong>Whatever HT is, Intel isn't a part of it, so I imagine that these people are gunning for Intel.
Jet</strong><hr></blockquote>
hmmm... IBM's not a member?
Will Apple continue to use it's own chipset, or will it contract nVidia to develop a Macintosh nForce?
Barto
IF Apple ever uses either of these technologies, it will be no sooner than 12-18 months after they have been offered on Wintel boxes.
I simply do not see Apple jumping from mobo technology that is several years out of date, into a mobo that is bleeding edge. It's totally uncharacteristic of Apple.
Whether this technology (if used) makes it into the falls P-Macs or next springs in the question that drives us...
If you read the article you would see that the new members are:
[quote]The new members are Actel Corp., American Megatrends, ATI Technologies, Cavium Networks, Dolphin Technology, Multinode Microsystems, PLX Technology, Primarion, Silicon Integrated Systems (SiS), Tektronix, and VIA Technologies.
<hr></blockquote>
[ 07-15-2002: Message edited by: Eskimo ]</p>
nForce2 has NOT been announced. It will be announced on the 17th. It is widely believed to supprt DDR bandwidths at 200mhz (400mhz effective) and USB2.
Before you start reading that date as if it was a magical tea-leaf, that is also the same date as R300's annoucement.
Another interesting thought the nForce has dual 64 bit DDR controllers allowing it to create a 128 bit memory bus. However the bandwidth is wasted because the Athlon's FSB is limited to 133 Mhz (according to the article). SO then if Apple were to integrate multiple DDR controllers in their next board as nVidia is doing in the nForce and video cards and ATI is doing in vid cards, one of the keys is going to be having a wide enough processor<->chipset bus. As the reg has pointed out, wider is better. If Apple can build a suitably fast and wide processor interface into their next processors they could do some really powerful things....
No I do not think the next PowerMacs will have an nForce chipset but nVidia is dealing with a lot of the same issues Apple is and the decisions they make are no doubt being studied in Cupertino.
<strong>Another interesting thought the nForce has dual 64 bit DDR controllers allowing it to create a 128 bit memory bus. However the bandwidth is wasted because the Athlon's FSB is limited to 133 Mhz (according to the article). SO then if Apple were to integrate multiple DDR controllers in their next board as nVidia is doing in the nForce and video cards and ATI is doing in vid cards, one of the keys is going to be having a wide enough processor<->chipset bus. As the reg has pointed out, wider is better. If Apple can build a suitably fast and wide processor interface into their next processors they could do some really powerful things....</strong><hr></blockquote>
It's not wasted when the onboard video is used or textures overflow from the video memory in an graphics card.
Barto
<strong>Face up to reality: Apple is not going to implement something like RIO or HT anytime soon. These are both NEW technologies, and since when has Apple led the industry in offering bleeding edge tech in their towers?
I simply do not see Apple jumping from mobo technology that is several years out of date, into a mobo that is bleeding edge. It's totally uncharacteristic of Apple.</strong><hr></blockquote>
Uh, no. Actually, just the opposite.
Apple *does* jump like this. What they *don't* do is the smooth steady path. The jumps to PPC, to G3, the DSP in the 840AV, Firewire, USB, now Bluetooth, and some of the bus improvements over the years have actually been fairly innovative.
Certainly lately Mot has been screwing this whole strategy to some degree, but keep in mind that prior to DDR 18 months ago, Apple was fairly competitive bus-wise, and the holdup was MHz, but they had just taken a leap with Altivec that did produce results at the cost of getting hosed by Mot.
Apple is clearly not bothering to invest dollars in small incremental improvements only to *still* be behind Wintel. My guess is that they are looking 24-36 months out on their design (as they did with iMac) with the intention of either leapfrogging Wintel, or coming roughly in parity with it. By all accounts we are in the closing days of that window with PowerMac and that we'll see some substantial improvement either in August or early next year.
<strong>
It's not wasted when the onboard video is used or textures overflow from the video memory in an graphics card.
Barto</strong><hr></blockquote>
Yes, but I think most PowerMac users would have kittens if the next PowerMac had integrated video, so that leaves a kinda' thin rationalization for all that extra bandwidth. I think it's kinda' funny how everyone's been trash talking the XServes DDR implementation cause the processor doesn't get the full benefit of the Bus. It seems like Apple isn't alone with this issue (though AMDs Processor<->memory bandwidth is still higher). One thing I rogot to mention, AMD Zone hypothesized that with a dual processor design all that extra bandwidth would start to make sense.
One other surprise for me in the Anandtech review was it seems like Hypertransport is only being used to ling up the chipset, the Processor is still on a tight bus. I had thought the reason we were all begging for RapidIO or Hypertransport was to speed up the processor<->chipset link, is this an nVidia implementation issue or does Hypertransport have nothing to do with the processor<->motherboard interface?
<strong>Yes, but I think most PowerMac users would have kittens if the next PowerMac had integrated video, so that leaves a kinda' thin rationalization for all that extra bandwidth. I think it's kinda' funny how everyone's been trash talking the XServes DDR implementation cause the processor doesn't get the full benefit of the Bus. It seems like Apple isn't alone with this issue (though AMDs Processor<->memory bandwidth is still higher). One thing I rogot to mention, AMD Zone hypothesized that with a dual processor design all that extra bandwidth would start to make sense.
One other surprise for me in the Anandtech review was it seems like Hypertransport is only being used to ling up the chipset, the Processor is still on a tight bus. I had thought the reason we were all begging for RapidIO or Hypertransport was to speed up the processor<->chipset link, is this an nVidia implementation issue or does Hypertransport have nothing to do with the processor<->motherboard interface?</strong><hr></blockquote>
AMD processors that include HT interfaces are on the way, they just haven't arrived yet.
Multi-processors can only take advantage of increased memory bandwidth if they don't have to share the FSB. I'm not sure about the Athlon, but the G4's must share their FSB for bus snooping reasons.
Even AGP slot based video cards benefit from excess memory bandwidth that the system's processor(s) cannot use... remember that the video card can do reads from main memory across the AGP bus. AGP4x is about 1GB/sec and AGP8x is 2 GB/sec, so that can easily use up the excess bandwidth. With Quartz Extreme the GPU will actually be doing this all the time, whereas currently there is almost no use of the AGP-read capability.
<strong>This reminds me of the DSPs in the memory controller Moki was talking about <a href="http://www.anandtech.com/chipsets/showdoc.html?i=1654&p=4"; target="_blank">Dynamic Adaptive Speculative preprocessr</a> . So the concept seems viable especially for applications for moving big blocks of data around?
</strong><hr></blockquote>
I think you're confused... nVidia's DASP is doing no processing, it is just guessing at what memory will need to be read next. The "mini-DSPs" that Moki was talking about are actually small processors that modify data in the chipset rather than in the processor. Very different... but not entirely dissimilar to the graphics and audio capabilities that nVidia has in their nForce chipsets.
[quote]<strong>
No I do not think the next PowerMacs will have an nForce chipset but nVidia is dealing with a lot of the same issues Apple is and the decisions they make are no doubt being studied in Cupertino.</strong><hr></blockquote>
Apple has been doing chipsets a long time, and I'm pretty sure they're keeping up to date in other developments in the industry. I'm also pretty sure that they aren't going to use somebody else's... especially when Apple's are really quite good. Moki's comments and the Racyer patents seem to hint at Apple putting some computing power into the chipset, which makes some sense when you realize that that is the part of the silicon Apple actually controls -- as opposed to the CPU which they just buy from somebody else. I'm dubious about putting DSPs into the system, but if it is along the lines outlined in the Racyer patents then it gets much more interesting... especially if they do some work to make them easier for the developers to program & controller.
<strong>
the DSP in the 840AV</strong><hr></blockquote>
DSP != DASP, two totally different things.