We'll see 3GHz when IBM produces 3GHz CPUs in quantity, not sooner. I think it's pretty clear from the G5 introduction keynote that Steve loves blowing the competition away, and I don't see how he'll turn down an opportunity to remove as much ambiguity around that claim as possible. If the hardcore PC performance writers extolled the top-end PowerMac as the machine to beat, period, Apple would gain credibility they haven't had in about a decade
A fact born out by the PC Mag award for best computer and the extensive coverage in PC, Mac and Internet tech' press.
The G5 is a quality, world class, cutting edge product with untouchable design.
Remarkable. And it is only the beginning of a new generation...
After reading this board for a long time, I must take a moment to thank you for your decorum and respectful post. I don't know if it is just the holiday season or what... but I, for one, appreciate your kind and tactful approach to expressing your views.
"Kind words can be short and easy to speak, but their echoes are truly
I owe you a sincere public apology for the way you have been dragged into a futile discussion. I have always appreciate your postings and have learned something on many occasions. You seem to keep well informed about computers, which is my interest in reading these forums. So, after you made the above statement, I realize you know a lot, but electrical network analysis is not your forte. It appears you had a basic misunderstanding when you wrote that post, and you may like to know about it. I certainly would if it were me.
Unfortunately, your post became part of a debate here, so I think it is only fair for me to give you a much more complete answer than my original reply. You appear to simplify the processor as a "black box" to facilitate discussion. I find that to be a typical way engineers get cumbersome details out of the way so they can focus on simple issues. Otherwise, we are caught up in technicalities that don't get to the heart of the matter.
In this case, the black box is a collection of transistors, represented by connected resistors. It obeys a simple law, E = I x R, voltage is current times resistance. You appear to believe that adding transistors would increase resistance (R) and therefore the processor voltage (E) would need to be higher to supply the required current (I). This would be true if the resistors were in series, or connected in a daisy chain fashion. In fact, they are connected in parallel, each one going across the power supply terminals. In this case, total resistance is not the sum of the individual resistors.
A resistor has another characteristic that is called conductance, represented by G. It is equal to the reciprocal of resistance, G = 1 / R. In the case of parallel connect components, the total conductance (G) is equal to the sum of the individual elements. When you go through the math, you discover that with parallel connected components the resistance goes down when you add more parts. E = I x R still holds. So when R is less, and the supply voltage for the chip (E) stays the same, the current (I) increases, which increases power. Power = E x I.
I hope this is helpful. It is my interpretation of what you posted, although you may mean something entirely different that I don't see.
No need to apologize. This isn't exactly my field, I am a computer scientist not an electrical engineer. So reading the debate has been educational to me. That is the point of all this, isn't it? I think so. SO thanks to all of you who have kept the debate going, it has peaked my curiosity in this field.
As far as my statement goes, it was a generalization, but I can't take credit for it. My source was an IBM Engineer, a PHD actually, who wrote a research paper on dynamically changing voltage in order to reduce heat. He probably made the generalization for the sake of the general reader. I don't think anyone can argue that it was nothing more than a generalization and as everyone know generalizations always fail under scrutiny, but they do serve their purpose to to not get bogged down in the details for a non disciplined discussion.
No need to apologize. This isn't exactly my field, I am a computer scientist not an electrical engineer. So reading the debate has been educational to me. That is the point of all this, isn't it? I think so. SO thanks to all of you who have kept the debate going, it has peaked my curiosity in this field.
As far as my statement goes, it was a generalization, but I can't take credit for it. My source was an IBM Engineer, a PHD actually, who wrote a research paper on dynamically changing voltage in order to reduce heat. He probably made the generalization for the sake of the general reader. I don't think anyone can argue that it was nothing more than a generalization and as everyone know generalizations always fail under scrutiny, but they do serve their purpose to to not get bogged down in the details for a non disciplined discussion.
cz rulz!! ee sucks!! kill all those electrical engineers.
if theres any dynamically chanign voltage, i would imagine it to be for individual cmos gates, etc, where transistors can be connected in series.for example , if u have a large fan in NAND gate, you are goign to get lots of NMOS in series so large eq resistance. if you have a low resistance gate with small as shit fan in, you can feed a lower voltage to it.
cz rulz!! ee sucks!! kill all those electrical engineers.
if theres any dynamically chanign voltage, i would imagine it to be for individual cmos gates, etc, where transistors can be connected in series.for example , if u have a large fan in NAND gate, you are goign to get lots of NMOS in series so large eq resistance. if you have a low resistance gate with small as shit fan in, you can feed a lower voltage to it.
Of course, but you're forgetting the quantum delineation coefficients.
I can't seem to find the original quote, but I came across this in my past research,
In the design of pipelined processors, the hardware in each stage is optimized by restructuring logic and tuning transistor sizes to meet the cycle requirement. The tighter the delay budget, the greater the parallelism required at the gate level and the larger the transistor sizes needed, which leads to higher power.
It is clear to me, however, that "the dynamic power consumed in a chip is the sum of the power of all switching nodes."
But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
I can't seem to find the original quote, but I came across this in my past research,
In the design of pipelined processors, the hardware in each stage is optimized by restructuring logic and tuning transistor sizes to meet the cycle requirement. The tighter the delay budget, the greater the parallelism required at the gate level and the larger the transistor sizes needed, which leads to higher power.
It is clear to me, however, that "the dynamic power consumed in a chip is the sum of the power of all switching nodes."
But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
you answered your own question:
"the dynamic power consumed in a chip is the sum of the power of all switching node"
. . . But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
I suspect that mmicist knows more about this matter than any of us. I believe his succinct comment explains it very well.
"Nonetheless it is axiomatic that all power dissipation is resistive, how you analyse it depends on how much you know about the circuit and how it operates, but that is a different matter."
To expand a little, the mechanism that produces heat is current flowing through the resistive component of the transistors. However, to figure out what this heat will be, it is useful to calculate energy stored by these semiconductor switches. This energy is responsible for the heat producing current flow.
I suspect that mmicist know more about this matter than any of us. I believe his succinct comment explains it very well.
"Nonetheless it is axiomatic that all power dissipation is resistive, how you analyse it depends on how much you know about the circuit and how it operates, but that is a different matter."
To expand a little, the mechanism that produces heat is current flowing through the resistive component of the transistors. However, to figure out what this heat will be, it is useful to calculate energy stored by these semiconductor switches. This energy is responsible for the heat producing current flow.
heh. the engineer wouldnt care how the power is dissipated. engineer only want a model tat makes it easy to calculate the power dissipated.
I can't seem to find the original quote, but I came across this in my past research,
In the design of pipelined processors, the hardware in each stage is optimized by restructuring logic and tuning transistor sizes to meet the cycle requirement. The tighter the delay budget, the greater the parallelism required at the gate level and the larger the transistor sizes needed, which leads to higher power.
It is clear to me, however, that "the dynamic power consumed in a chip is the sum of the power of all switching nodes."
But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
Just how detailed an explanation do you want?
The simple version first then.
Important note) Capacitors do not themselves dissipate power (voltage and current are always out of phase). Only resistive elements can dissipate power.
For so-called dynamic power, consider the input of a (logic) gate being driven by some other circuit. First the input of the (logic) gate consists of the (control) gates of a number of transistors, which is an almost purely capacitive load. The input is controlled by a pair of transistors, one of which is connected to voltage high, and the other connected to voltage low. In the steady state one transistor is on, and the other is off.
When the logic switches the two driving transistors switch, and current flows on or off the capacitor through the newly on transistor. This current flows through the channel of the transistor, which is resistive, and hence dissipates power. However, the power dissipated is not directly controlled by the resistance, but by the capacitance, and the voltage range, which control the total charge moved around.
There is another element of dynamic power dissipated, which is becoming more important at shorter sizes, which is the current that flows through the two transistors whilst both are switching and there is a direct resistive path from high voltage to low voltage. It so happens that this current is approxiamtely proportional to the gate capacitances of the transistors, and is usually approximated by a fudge factor correction to the capacitance based calculation.
On top of this, and related to the original post, is that the voltage you need to use to make the transistors work properly depends on the size of the transistors, a shorter gate length means a lower voltage is required to achieve the electric field under the gate which will give velocity saturation of the carriers. This is complicated by the fact that the voltage must also be high enough to cope with the variation in threshold voltage of transistors (the input voltage at which the transistor switches from on to off or vice-versa) and current processes run at much higher voltages than would otherwise be necessary because there is considerable variation in threshold voltage accross a wafer or even a chip.
The original post mentioned that reducing the size of the transistors would increase the channel resistance, and hence require a higher voltage, leading to no reduction in power dissipation, but this doesn't take into account the simultaneous scaling of the capacitances etc., nor the fact that the resistance doesn't control the total charge moved around per state change, but just the current, (which controls the speed of switching). So that reducing the process size does reduce the power dissipated.
Much more interesting at very short gate lengths and thin gate dielectrics are the leakage currents which give rise to both dynamic and static power dissipation, and controlling these is probably the most difficult part of developing new processes.
The more complex version isn't really suited to this board, but ask if you want it.
heh. the engineer wouldnt care how the power is dissipated. engineer only want a model tat makes it easy to calculate the power dissipated.
Some of we engineers are the ones who develop these models, and we need to know what is really happening. It is also important for all engineers to know the limitations of the models they use, so that can recognise the cases when they don't apply.
Some of we engineers are the ones who develop these models, and we need to know what is really happening. It is also important for all engineers to know the limitations of the models they use, so that can recognise the cases when they don't apply.
michael
the majority of engineers just use the models and are given quantitative limits to the models.
the majority of engineers just use the models and are given quantitative limits to the models.
Thankfully the majority of engineers don't think like that. You aren't a graduate or ever going to be a particularly good engineer if you believe that. Any engineer past 2nd or 3rd year uni will be able to talk to you about the importance of understanding the assumptions and limitations a model is built on and why more complex models are necessary.
if u have a large fan in NAND gate, you are goign to get lots of NMOS in series so large eq resistance. if you have a low resistance gate with small as shit fan in, you can feed a lower voltage to it.
This is complicated by the fact that the voltage must also be high enough to cope with the variation in threshold voltage of transistors (the input voltage at which the transistor switches from on to off or vice-versa) and current processes run at much higher voltages than would otherwise be necessary because there is considerable variation in threshold voltage accross a wafer or even a chip.
Ok, it is making more sense. Now, regarding the statement of yours I quoted above, IBM seems to have a solution for. They developed a technique they call "Voltage Islands" within a chip design such that the chips internals are divided into sections based on their voltage needs. This way maybe the core processor will be at 1.2V and the FPU will be at 1V and if there is a UART it can be at less than 1V, etc. The numbers are only for illustrative purposes. Am I understanding this correctly? The way I read IBM's research paper, IBM is basically designing a chip to mimic a Motherboard design but eliminating much of the expensive off chip communications, basically a SOC. In addition, they are able to dynamically adjust the voltage based on frequency adjustments giving them a quadratic decrease in power as well as heat. Am I making sense? Do I understand this correctly?
Comments
We'll see 3GHz when IBM produces 3GHz CPUs in quantity, not sooner. I think it's pretty clear from the G5 introduction keynote that Steve loves blowing the competition away, and I don't see how he'll turn down an opportunity to remove as much ambiguity around that claim as possible. If the hardcore PC performance writers extolled the top-end PowerMac as the machine to beat, period, Apple would gain credibility they haven't had in about a decade
A fact born out by the PC Mag award for best computer and the extensive coverage in PC, Mac and Internet tech' press.
The G5 is a quality, world class, cutting edge product with untouchable design.
Remarkable. And it is only the beginning of a new generation...
Lemon Bon Bon
Originally posted by Jubelum
After reading this board for a long time, I must take a moment to thank you for your decorum and respectful post. I don't know if it is just the holiday season or what... but I, for one, appreciate your kind and tactful approach to expressing your views.
"Kind words can be short and easy to speak, but their echoes are truly
endless. - Mother Theresa"
Kudos to you. 8)
i second that
Originally posted by Lemon Bon Bon
The G5 is a quality, world class, cutting edge product with untouchable design.
Remarkable. And it is only the beginning of a new generation...
Phil Schiller couldn't have said it better himself.
Originally posted by Lemon Bon Bon
A fact born out by the PC Mag award for best computer and the extensive coverage in PC, Mac and Internet tech' press.
The G5 is a quality, world class, cutting edge product with untouchable design.
Remarkable. And it is only the beginning of a new generation...
Lemon Bon Bon
A G5 is like Prozak.
Look what it did with the mind of LBB.
One G5 and he's writing marketing lyrics for Apple
Bigc
Say, I always wondered why the 'Bigc' has a little 'c' in his handle...
Lemon Bon Bon
Originally posted by snoopy
stingerman,
I owe you a sincere public apology for the way you have been dragged into a futile discussion. I have always appreciate your postings and have learned something on many occasions. You seem to keep well informed about computers, which is my interest in reading these forums. So, after you made the above statement, I realize you know a lot, but electrical network analysis is not your forte. It appears you had a basic misunderstanding when you wrote that post, and you may like to know about it. I certainly would if it were me.
Unfortunately, your post became part of a debate here, so I think it is only fair for me to give you a much more complete answer than my original reply. You appear to simplify the processor as a "black box" to facilitate discussion. I find that to be a typical way engineers get cumbersome details out of the way so they can focus on simple issues. Otherwise, we are caught up in technicalities that don't get to the heart of the matter.
In this case, the black box is a collection of transistors, represented by connected resistors. It obeys a simple law, E = I x R, voltage is current times resistance. You appear to believe that adding transistors would increase resistance (R) and therefore the processor voltage (E) would need to be higher to supply the required current (I). This would be true if the resistors were in series, or connected in a daisy chain fashion. In fact, they are connected in parallel, each one going across the power supply terminals. In this case, total resistance is not the sum of the individual resistors.
A resistor has another characteristic that is called conductance, represented by G. It is equal to the reciprocal of resistance, G = 1 / R. In the case of parallel connect components, the total conductance (G) is equal to the sum of the individual elements. When you go through the math, you discover that with parallel connected components the resistance goes down when you add more parts. E = I x R still holds. So when R is less, and the supply voltage for the chip (E) stays the same, the current (I) increases, which increases power. Power = E x I.
I hope this is helpful. It is my interpretation of what you posted, although you may mean something entirely different that I don't see.
No need to apologize. This isn't exactly my field, I am a computer scientist not an electrical engineer. So reading the debate has been educational to me. That is the point of all this, isn't it? I think so. SO thanks to all of you who have kept the debate going, it has peaked my curiosity in this field.
As far as my statement goes, it was a generalization, but I can't take credit for it. My source was an IBM Engineer, a PHD actually, who wrote a research paper on dynamically changing voltage in order to reduce heat. He probably made the generalization for the sake of the general reader. I don't think anyone can argue that it was nothing more than a generalization and as everyone know generalizations always fail under scrutiny, but they do serve their purpose to to not get bogged down in the details for a non disciplined discussion.
Originally posted by stingerman
No need to apologize. This isn't exactly my field, I am a computer scientist not an electrical engineer. So reading the debate has been educational to me. That is the point of all this, isn't it? I think so. SO thanks to all of you who have kept the debate going, it has peaked my curiosity in this field.
As far as my statement goes, it was a generalization, but I can't take credit for it. My source was an IBM Engineer, a PHD actually, who wrote a research paper on dynamically changing voltage in order to reduce heat. He probably made the generalization for the sake of the general reader. I don't think anyone can argue that it was nothing more than a generalization and as everyone know generalizations always fail under scrutiny, but they do serve their purpose to to not get bogged down in the details for a non disciplined discussion.
cz rulz!! ee sucks!! kill all those electrical engineers.
if theres any dynamically chanign voltage, i would imagine it to be for individual cmos gates, etc, where transistors can be connected in series.for example , if u have a large fan in NAND gate, you are goign to get lots of NMOS in series so large eq resistance. if you have a low resistance gate with small as shit fan in, you can feed a lower voltage to it.
Originally posted by Nr9
cz rulz!! ee sucks!! kill all those electrical engineers.
if theres any dynamically chanign voltage, i would imagine it to be for individual cmos gates, etc, where transistors can be connected in series.for example , if u have a large fan in NAND gate, you are goign to get lots of NMOS in series so large eq resistance. if you have a low resistance gate with small as shit fan in, you can feed a lower voltage to it.
Of course, but you're forgetting the quantum delineation coefficients.
(Sorry, all this stuff goes way over my head...)
In the design of pipelined processors, the hardware in each stage is optimized by restructuring logic and tuning transistor sizes to meet the cycle requirement. The tighter the delay budget, the greater the parallelism required at the gate level and the larger the transistor sizes needed, which leads to higher power.
It is clear to me, however, that "the dynamic power consumed in a chip is the sum of the power of all switching nodes."
But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
Originally posted by stingerman
I can't seem to find the original quote, but I came across this in my past research,
In the design of pipelined processors, the hardware in each stage is optimized by restructuring logic and tuning transistor sizes to meet the cycle requirement. The tighter the delay budget, the greater the parallelism required at the gate level and the larger the transistor sizes needed, which leads to higher power.
It is clear to me, however, that "the dynamic power consumed in a chip is the sum of the power of all switching nodes."
But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
you answered your own question:
"the dynamic power consumed in a chip is the sum of the power of all switching node"
Originally posted by stingerman
. . . But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
I suspect that mmicist knows more about this matter than any of us. I believe his succinct comment explains it very well.
"Nonetheless it is axiomatic that all power dissipation is resistive, how you analyse it depends on how much you know about the circuit and how it operates, but that is a different matter."
To expand a little, the mechanism that produces heat is current flowing through the resistive component of the transistors. However, to figure out what this heat will be, it is useful to calculate energy stored by these semiconductor switches. This energy is responsible for the heat producing current flow.
Originally posted by snoopy
I suspect that mmicist know more about this matter than any of us. I believe his succinct comment explains it very well.
"Nonetheless it is axiomatic that all power dissipation is resistive, how you analyse it depends on how much you know about the circuit and how it operates, but that is a different matter."
To expand a little, the mechanism that produces heat is current flowing through the resistive component of the transistors. However, to figure out what this heat will be, it is useful to calculate energy stored by these semiconductor switches. This energy is responsible for the heat producing current flow.
heh. the engineer wouldnt care how the power is dissipated. engineer only want a model tat makes it easy to calculate the power dissipated.
Originally posted by stingerman
I can't seem to find the original quote, but I came across this in my past research,
In the design of pipelined processors, the hardware in each stage is optimized by restructuring logic and tuning transistor sizes to meet the cycle requirement. The tighter the delay budget, the greater the parallelism required at the gate level and the larger the transistor sizes needed, which leads to higher power.
It is clear to me, however, that "the dynamic power consumed in a chip is the sum of the power of all switching nodes."
But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
Just how detailed an explanation do you want?
The simple version first then.
Important note) Capacitors do not themselves dissipate power (voltage and current are always out of phase). Only resistive elements can dissipate power.
For so-called dynamic power, consider the input of a (logic) gate being driven by some other circuit. First the input of the (logic) gate consists of the (control) gates of a number of transistors, which is an almost purely capacitive load. The input is controlled by a pair of transistors, one of which is connected to voltage high, and the other connected to voltage low. In the steady state one transistor is on, and the other is off.
When the logic switches the two driving transistors switch, and current flows on or off the capacitor through the newly on transistor. This current flows through the channel of the transistor, which is resistive, and hence dissipates power. However, the power dissipated is not directly controlled by the resistance, but by the capacitance, and the voltage range, which control the total charge moved around.
There is another element of dynamic power dissipated, which is becoming more important at shorter sizes, which is the current that flows through the two transistors whilst both are switching and there is a direct resistive path from high voltage to low voltage. It so happens that this current is approxiamtely proportional to the gate capacitances of the transistors, and is usually approximated by a fudge factor correction to the capacitance based calculation.
On top of this, and related to the original post, is that the voltage you need to use to make the transistors work properly depends on the size of the transistors, a shorter gate length means a lower voltage is required to achieve the electric field under the gate which will give velocity saturation of the carriers. This is complicated by the fact that the voltage must also be high enough to cope with the variation in threshold voltage of transistors (the input voltage at which the transistor switches from on to off or vice-versa) and current processes run at much higher voltages than would otherwise be necessary because there is considerable variation in threshold voltage accross a wafer or even a chip.
The original post mentioned that reducing the size of the transistors would increase the channel resistance, and hence require a higher voltage, leading to no reduction in power dissipation, but this doesn't take into account the simultaneous scaling of the capacitances etc., nor the fact that the resistance doesn't control the total charge moved around per state change, but just the current, (which controls the speed of switching). So that reducing the process size does reduce the power dissipated.
Much more interesting at very short gate lengths and thin gate dielectrics are the leakage currents which give rise to both dynamic and static power dissipation, and controlling these is probably the most difficult part of developing new processes.
The more complex version isn't really suited to this board, but ask if you want it.
michael
Originally posted by Nr9
heh. the engineer wouldnt care how the power is dissipated. engineer only want a model tat makes it easy to calculate the power dissipated.
Some of we engineers are the ones who develop these models, and we need to know what is really happening. It is also important for all engineers to know the limitations of the models they use, so that can recognise the cases when they don't apply.
michael
Originally posted by mmicist
Some of we engineers are the ones who develop these models, and we need to know what is really happening. It is also important for all engineers to know the limitations of the models they use, so that can recognise the cases when they don't apply.
michael
the majority of engineers just use the models and are given quantitative limits to the models.
Originally posted by Nr9
the majority of engineers just use the models and are given quantitative limits to the models.
Thankfully the majority of engineers don't think like that. You aren't a graduate or ever going to be a particularly good engineer if you believe that. Any engineer past 2nd or 3rd year uni will be able to talk to you about the importance of understanding the assumptions and limitations a model is built on and why more complex models are necessary.
Originally posted by Nr9
if u have a large fan in NAND gate, you are goign to get lots of NMOS in series so large eq resistance. if you have a low resistance gate with small as shit fan in, you can feed a lower voltage to it.
They put little FANS on the processor??
No wonder they use so much power!
-- Mark
(P.S. yes, i'm kidding)
Originally posted by mmicist
This is complicated by the fact that the voltage must also be high enough to cope with the variation in threshold voltage of transistors (the input voltage at which the transistor switches from on to off or vice-versa) and current processes run at much higher voltages than would otherwise be necessary because there is considerable variation in threshold voltage accross a wafer or even a chip.
Ok, it is making more sense. Now, regarding the statement of yours I quoted above, IBM seems to have a solution for. They developed a technique they call "Voltage Islands" within a chip design such that the chips internals are divided into sections based on their voltage needs. This way maybe the core processor will be at 1.2V and the FPU will be at 1V and if there is a UART it can be at less than 1V, etc. The numbers are only for illustrative purposes. Am I understanding this correctly? The way I read IBM's research paper, IBM is basically designing a chip to mimic a Motherboard design but eliminating much of the expensive off chip communications, basically a SOC. In addition, they are able to dynamically adjust the voltage based on frequency adjustments giving them a quadratic decrease in power as well as heat. Am I making sense? Do I understand this correctly?