Power4 or 5 versus G4 74XX
Altivec, full speed L2 and newly implementation of L3 are key features of the current G4 lines. But for the higher end IBM Power series, very little information are published. I wonder what are the major differences? As for most posts that have mentioned the Power4 series and the soon to be released a cut down version Power4 with SIMD, bandwidths have been heavily mentioned to reduce the bottlenecks between the processor and its other connecting devices But what did IBM do to increase bandwidth, did they just jack up the speed by utilizing DDR, rambus or they just simply design multiple buses to ease traffic in order to for the processor to crunch more data? As for other enhancements of the PowerX chips, I hear about multiple cores alot, did the chip contain more than 1 processor inside and what are 8 way symmetric process that they have been mentioning. Well, my major question is how these features leapfrog the current PM line and how much better compare to those new Pentium 4.
Comments
<strong>Altivec, full speed L2 and newly implementation of L3 are key features of the current G4 lines. But for the higher end IBM Power series, very little information are published. I wonder what are the major differences? As for most posts that have mentioned the Power4 series and the soon to be released a cut down version Power4 with SIMD, bandwidths have been heavily mentioned to reduce the bottlenecks between the processor and its other connecting devices But what did IBM do to increase bandwidth, did they just jack up the speed by utilizing DDR, rambus or they just simply design multiple buses to ease traffic in order to for the processor to crunch more data? As for other enhancements of the PowerX chips, I hear about multiple cores alot, did the chip contain more than 1 processor inside and what are 8 way symmetric process that they have been mentioning. Well, my major question is how these features leapfrog the current PM line and how much better compare to those new Pentium 4.</strong><hr></blockquote>
Hmm a lot of questions :
first of all the rumors said that IBM will supply the next generation of highend desktop chips for Apple with a derived chip based on the power4 line.
IBM said that he work on a simplified monocore version of the power 4 (which is dual core) , and IBM also stated that he works on VMX aka Altivec (i found a pdf file of patents and one of it, they speak of VMX and vpermut.
The current power4 chip is a dual core 64 bit chip containing 174 millions transistors, consomming more than 100 watt, make on a 0,18 CMOS SOI process. The power 4 is more than a chip, it's a system, allowing to linK 4 power 4 chips in a very efficient way creating a
8 way full symetrical system Each core is a superscalar chip with 8 units (higly pipelined : 14) wich is able to manage up to 5 instruction per cycle. The core are linked by a very efficient link working at half speed of the chip. There is large amount of cache (total of 128 KB L1 cache and shared 1,44 MB L2 cache and a huge L3 controller : up to 128 MB ), the power 4 includes many technology of error corrections (from memory to PCI bus) and I/O technologies..;
The important thing is that the core of a power 4 (30 millions of transistors), is much more powerfull than the core of the G4 and much scalable in speed (the power 4 on 0,18 process is already at 1,3 ghz) due to the deeper pipelining.
The rumors are supposing that the next chip made by IBM for desktop (let's call him the power VMX) will be a single core power4 with a VMX unit (an altivec one, but you can bet that IBM will make an even better altivec unit than the 7455 one) with rapid I/O stuff in order to control DDR memory for example. The L2 cache will be smaller (512 to 1024 KB) and perhpas there would not be an L3 cache (but this kind of things is too difficult to guess ) in order to make some economies.
The chip will be made under 0,13 SOI process or better 0,09 process, bringing the room for very high clock speed. (up to 2 ghz on 0,13)
according to IBM the power 4 project take 4 years to elaborate, that's why i am so confident that they will use it's core with the addition of an altivec unit. The Power 4 core is the result of a very important R&D investissement : he was made to be at the top of the art, and to have enough room to increase in clock speed, and to be multicore compatible. IBM will not waste his time to make a new core for Apple, he will adapt this core for his new desktop line. I don't know what kind of memory controller IBM will use, but i am ready to bet that the mobo will use DDR ram, and i think that DDR 333 will be used.
I bet that you have understand that this chip will be very different from a pentium 4 : it's a 64 bits chip, less pipelined made for raw power and not for the clock speed. You should better compare it to the new chip from MOT the opteron. In Intel word you should compare the power chips with the itanium chips.
There is just one question for a "not so deep im cpu tec guy" like me:
What is the rationale for making more pipelined cpus running at higher clock speed?
The tradeoff is that the longer the pipeline, the more time (CPU cycles) you waste when a branch is mispredicted. Modern processors predict the results of conditionals (things like if...then...else), and start running with the prediction, so the "then" or "else" code starts execution immediately after the condition instruction.
Without branch predictions the processor would stall until the result of the conditional instruction was known, several stages and clock cycles down the pipeline, wasting time. Branch predictions keep the CPU occupied while waiting for branch results, and cut down stalling when they're correct.
Of course, the branch predictions may be wrong, which causes problems for long pipeline CPUs. If the prediction was wrong, a CPU with many pipeline stages has to throw away more and has wasted more clock cycles than a shorter pipelined CPU. This reduces the efficiency of long pipelines, but longer pipelines do allow more cycles in a given time. CPUs with long pipelines therefore tend to have more complex branch prediction mechanisms, which take up some of the transistor count.
Summary:
-long pipelines can be clocked faster
-but are penalised heavily by branch mis-predictions.
I'm sure there's more to the long vs. short pipeline argument.. Branch prediction is quite complex: I'd recommend Ars for more on CPU theory.
[ 08-09-2002: Message edited by: Stoo ]</p>
Thanks Stoo!
I have it.
Shorter piplines = more complex stages = slower stages = lower clock speed.
OK.