AMD's Hammer gets delayed again.....

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  • Reply 21 of 26
    [quote]Originally posted by Junkyard Dawg:

    <strong>



    No way! Why should I change my name, he's the one who sucks!!!



    [ 09-13-2002: Message edited by: Junkyard Dawg ]</strong><hr></blockquote>





    Excuse me, I beleive you have my stapler... I could set the building on fire...
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  • Reply 22 of 26
    [quote]Originally posted by xype:

    <strong>

    Basically, from what I know, x86-64 runs 32bit code pretty well which means _if_ people upgrade to a 64bit CPU they don't need to run 32bit code trough much of a emulation process which in turn means faster 32bit code. And since most code today is 32 bit (and a chunk of it will likely stay so) I see the trnasition being less painful when taking the x86-64 route.



    So whatever technology is better is not the question, the question is what technology the customer will find easier to migrate to (think USB/FireWire).</strong><hr></blockquote>



    Yes, the Intel IA-64 hasn't been very impressive in emulating x86-32 code, while AMD's x86-64 can run it natively (much like a 64-bit PPC could run 32-bit PPC code natively and at full speed).



    IA-64 sucks and Intel is using its muscle and influence to ensure that industry people who think that don't speak it allowed. Look at the head of technologies at NEC... he leveled some criticism at IA-64 and within 3 months he's the former head of technologies at NEC.



    Even HP doesn't really seem to be fully on-board Intel's bandwagon on this one, and they started it!
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  • Reply 23 of 26
    Hmmm, hopefully by the time Intel can get the Itanic 2 to market in any meaningful form...and AMD's Hammer, due late 1st quarter 2003...it won't be long in the grand scheme of things that Apple can get its own 64 bit retort out a mere several months after the Hammer is shipping?



    In a 3 three fight of Intel, AMD and IBM...I know which I'd place my money on.



    With the 'Power' line, Apple gives its users a genuine and powerful road map and a dollop of security in the CPU wars. The Power fpu is amazing. For Lightwave smack heads like moi, it's got me juicin' already. It's a sharp contrast to the position Moto's 'ball droppin' has put Apple in over the last few years.



    IBM gives Apple the chance to scythe down the opposition in one fell swoop.



    Intel's Itanic 2 is rockin'. It's stumbled and bellyflopped into the market. (Wasn't it supposed to be out years ago?)



    AMD's Hammer has slipped and has slipped again!



    IBM are quietly going about their business with a 64 bit slimlined Power for a wider market...it's own workstations, server line, Linux and Apple and doubtless other oems.



    Apple, who've been suffering in the 'mhz' wars for the last several years get to play on a level playing field as the battlefield's focus moves to 64 bit. If Apple plays its cards right... Power vs Hammer vs Itanic 2 looks alot better than G4 (CONSUMER) vs Athlon XP vs P4 looks right now.



    And hey, won't the Powerlite have a higher mhz than the Itanic 2? Somebody shoot me, the irony is killing me



    Lemon Bon Bon



    [ 09-14-2002: Message edited by: Lemon Bon Bon ]



    [ 09-14-2002: Message edited by: Lemon Bon Bon ]</p>
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  • Reply 24 of 26
    programmer - excellent posts. You don't by chance ever visit the <a href="http://www.aceshardware.com/forum"; target="_blank">Aceshardware.com forums</a>, do you? If not, you might want to give them a try.



    Anyway, I agree with much of what you have written. The one thing that you wrote, however, that I'd like to add to is the compiler-dependent characteristic of INTC's implementation of IA-64.



    It may be true that the compiler writing is hideously complex, especially since the compiler has to generate it for a non-OoO chip. However, x86 compilers have been written and tweaked for a couple decades now. IA-64 is pretty darn new compared to that.



    I think that, given a smilar amount of time, there is a chance that the compiler folks will build very good compilers for the IA-64. If this happens, the parallelism of the Itanium family can be used for crunching more code more quickly as opposed to now, when it's being used (partially) to make up for compiler deficiencies.



    In any case, that's just from my limited knowledge on the subject. Sounds to me that you're much more familiar with this than I, however, so I'd be interested in hearing any corrections you'd make to my thoughts.



    neye



    [ 09-15-2002: Message edited by: neye_eve ]</p>
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  • Reply 25 of 26
    [quote]Originally posted by neye_eve:

    <strong>Anyway, I agree with much of what you have written. The one thing that you wrote, however, that I'd like to add to is the compiler-dependent characteristic of INTC's implementation of IA-64.



    It may be true that the compiler writing is hideously complex, especially since the compiler has to generate it for a non-OoO chip. However, x86 compilers have been written and tweaked for a couple decades now. IA-64 is pretty darn new compared to that.



    I think that, given a smilar amount of time, there is a chance that the compiler folks will build very good compilers for the IA-64. If this happens, the parallelism of the Itanium family can be used for crunching more code more quickly as opposed to now, when it's being used (partially) to make up for compiler deficiencies.



    In any case, that's just from my limited knowledge on the subject. Sounds to me that you're much more familiar with this than I, however, so I'd be interested in hearing any corrections you'd make to my thoughts.</strong><hr></blockquote>



    Take a look at the problems optimizing code for all of the x86 processors... the 386 and 486 are basically the same, and the AMD K5/K6 are pretty close to that. The Pentium introduced paired instructions. The Pentium II turned the whole instruction set on its head and required quite a different set of optimizations, and the Pentium III extended that to a few new instructions. The PentiumIV invalidates many the optimization rules for all previous chips (just look at the poor PIV performance in most software when it first was introduced). The Athlon is different again. Despite all the differences in how to make code run fast, at least it runs on all of the processors.



    The IA-64, however, is different. It has a much more complex execution model and so the difference between successive generations will be much greater than in the x86. There are a few areas where its not even clear whether the software built for one version will necessarily run on the next (I may be wrong on this, or it may have changed -- my knowledge on the IA-64 is quite faded). The more information a compiler has to have about a specific processor, the more wrong it is going to be about a different processor.



    The PowerPC suffers from this as well, but its not nearly so bad and the software will always run correctly between different chips (barring bugs in the chips and software, of course ). Also, optimizations for later chips usually result in good performance on earlier ones... I'm not aware of any generational difference like there are from PentiumIII -&gt; PentiumIV. Even the move to POWER-derived chips shouldn't invalidate the optimizations used on previous PPC chips. The same goes for the Hammer -- it should do a good job of running code built for the Athlon, and Hammer software that doesn't use new modes and instructions should run well on the Athlon.
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  • Reply 26 of 26
    bartobarto Posts: 2,246member
    All hail the mighty Programmer!
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