Developer Notes points to possible reason for delay
Apple has posted the G5 Xserve Developer Notes . One interesting tidbit is that the system controller is 130 nm, not 90 nm as widely rumoured.
Click on "Architecture", and then on "U3H Bridge and Memory Controller". It is near the bottom in the "Processor Bus" section.
Could this be the reason for the delay of PowerMacs? Since the Xserves are only using 2GHz parts, a new SC isn't really needed. But for faster chips, if they are having problems getting the system control on a 90nm process, it would make sense.
Click on "Architecture", and then on "U3H Bridge and Memory Controller". It is near the bottom in the "Processor Bus" section.
Quote:
The Xserve G5 system controller is built with state-of-the-art 130-nanometer, SOI technology.
The Xserve G5 system controller is built with state-of-the-art 130-nanometer, SOI technology.
Could this be the reason for the delay of PowerMacs? Since the Xserves are only using 2GHz parts, a new SC isn't really needed. But for faster chips, if they are having problems getting the system control on a 90nm process, it would make sense.
Comments
BTW: Thanks for the linkage to the Developer Notes.
Originally posted by Crusader
Yea, I don't think that the system controller has to be built using the same process as the chip it's communicating with.
That is a given since the Xserve are 90nm 970s but the system control is 130nm.
For a 3 Ghz G5 the system controller would only have to run at 1.5 Ghz. Holy crap the system controller will run at a higher speed than the G4 chips. That will be an excellent day indeed.
BTW: Thanks for the linkage to the Developer Notes.
There was a rumor going round that the current system control could only clock up to 1.1GHz. Do we know with certantity that the current system control can clock up to 1.5Ghz, and still run at a reasonable heat level?
Where we not debating and pondering an article about IBM producing a 90nm soc two months ago?
Could this be the same chip?
Just pondering, please correct me if I am wrong.
Originally posted by oldmacfan
Hmm,
Where we not debating and pondering an article about IBM producing a 90nm soc two months ago?
Could this be the same chip?
Just pondering, please correct me if I am wrong.
If I am not mistaken a SOC (system on a chip) and an SC (system controler) are two different beasts. So the fact that IBM is making 90nm SOC and 90nm 970s doesn't necessarily mean that they aren't having problems making 90nm system controlers for the 970.
Originally posted by kupan787
Apple has posted the G5 Xserve Developer Notes . One interesting tidbit is that the system controller is 130 nm, not 90 nm as widely rumoured.
Click on "Architecture", and then on "U3H Bridge and Memory Controller". It is near the bottom in the "Processor Bus" section.
Could this be the reason for the delay of PowerMacs? Since the Xserves are only using 2GHz parts, a new SC isn't really needed. But for faster chips, if they are having problems getting the system control on a 90nm process, it would make sense.
Well picked up kupan! it was ASSUMED that the SC chip would be fabbed with the CPU, of course the PMac nor the xServe require the new SC, as for a G5 Powerbook?, definetly.
Programmers explanation is more plausible than the spurious notions being thrown around?.
Originally posted by oldmacfan
Hmm,
Where we not debating and pondering an article about IBM producing a 90nm soc two months ago?
Could this be the same chip?
Just pondering, please correct me if I am wrong.
Yes we were. The IBM rep was quoted as saying they had just begun shipping 0.09µm SOC chips to Apple. So either
the rep was misquoted and meant SC or
the rep made a mistake during the interview and meant SC or
the rep was using industry accepted terminology(??) for SOC = SC or
Apple did order SOC processors for an undisclosed product or
the rep made a mistake and meant 0.13µm SOC or
the rep was misquoted and said 0.13µm SC or
or or or
pick your poison
Originally posted by Bigc
Keyword seems to be misquoted...
Which one? 0.13µm or SOC?
If SOC, then why the 0.13µm SC in the xServe?
If 0.13µm then where's the SOC chip going?
If both SOC and 0.13µm then the journalist should be required to go back to school.
this dissecting of the IBM quote could go on until WWDC, couldn't it? After all we need something to discuss with so many delays.