Just because it supports up to 6.4GBps bandwidth doesn't mean the memory must max the bus. Apple should use the least expensive/best performing ratio memory available at the time. If this spring, that's probably PC2700 (what the Macs use now throttled) and that provides 2.7GBps. If a bus can fully deliver that, it would be an accomplishment in and of itself. If a new PowerMac with GPUL is introduced in the summer/fall then you may be looking at a 400MHz flavor of DDR-II. Either way it will impress. Also I hear the actual theoretical bandwidth of the processor is 7.2GBps, but IBM quotes 6.4 after bus overhead is factored in. And as a note, RapidIO is notorious for large overhead.
And finally, and this is speculation, I think that IBM under estimated the speed of these chips. If the chip has a 16-18 stage pipeline on 130nm process it should do 2GHz out of the gate. Maybe it's hotspots in the silicon that make it clock at 1.8... Consider a G4 with a 7 stage pipeline and made on 180nm can manage 1.25GHz...
<strong>Just because it supports up to 6.4GBps bandwidth doesn't mean the memory must max the bus. Apple should use the least expensive/best performing ratio memory available at the time. If this spring, that's probably PC2700 (what the Macs use now throttled) and that provides 2.7GBps. If a bus can fully deliver that, it would be an accomplishment in and of itself. If a new PowerMac with GPUL is introduced in the summer/fall then you may be looking at a 400MHz flavor of DDR-II. Either way it will impress. Also I hear the actual theoretical bandwidth of the processor is 7.2GBps, but IBM quotes 6.4 after bus overhead is factored in. And as a note, RapidIO is notorious for large overhead.
And finally, and this is speculation, I think that IBM under estimated the speed of these chips. If the chip has a 16-18 stage pipeline on 130nm process it should do 2GHz out of the gate. Maybe it's hotspots in the silicon that make it clock at 1.8... Consider a G4 with a 7 stage pipeline and made on 180nm can manage 1.25GHz...</strong><hr></blockquote>
I think I saw the pipeline for the CPU was 8 or 10 (saw that somewhere) but each unit such as fp int vmx etc each have thier own # pipelines stages.
Also for those still hung up on SPEC numbers
[code]
SPECint_base2000
=================
242 G4 800Mhz
259 G4 867Mhz
306 G4 1000Mhz
937 GPUL 1800Mhz
=================
SPECfp_base
=================
147 G4 800Mhz
153 G4 867Mhz
187 G4 1000Mhz
1051 GPUL 1800Mhz
=================
</pre><hr></blockquote>
Found the numbers for 800 867 and 1000 on c'st (I think that was the site) Oh and anyone have numbers for the 1250Ghz cpu's?
forgive me if this has been touched on already, but let's assume that the article is correct and we don't see this processor for another year or so. what happens in the mean time? faster g4s in the form of the g4+? will it scale up enough, at least two more times? or perhaps moto still has the g5 ready to make an intro the first of next year to be relegated to a lower end solution once the 970 comes out?
it looks like the P4 will be pushing 4Ghz by the time the 970 rolls around. . . and 100 watts! of course the new computer will be a staple item in the cold new england states and further north.
[quote]Originally posted by running with scissors:
<strong>forgive me if this has been touched on already, but let's assume that the article is correct and we don't see this processor for another year or so. what happens in the mean time? faster g4s in the form of the g4+? will it scale up enough, at least two more times? or perhaps moto still has the g5 ready to make an intro the first of next year to be relegated to a lower end solution once the 970 comes out?</strong><hr></blockquote>
I'm wondering about this too. The PPC 970 sounds great, but 12-15 months is an awfully long time for Apple to keep tap dancing around system performance while saddled with the G4.
If Mot wasn't very motivated to improve the G4 for Apple to begin with, it would seem they'd now have even less motivation to provide Apple with something new over this next year. I suppose Apple might stick to Mot for iMacs and iBooks, and even TiBooks for awhile, with the 970s only going into top-of-the-line Power Macs and Xserves at first. But sooner or later it would seem Mot's on the way out.
Does anyone else see the 970 as indicitive of a bright future, but also see grim times until then?
<strong>I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.</strong><hr></blockquote>
I believe he extrapolated the 7.2 GBps theoretical maximum throughput from the 900 MHz clock of the FSB.
[quote]Originally posted by Programmer:
<strong>Linear scaling by clock rate isn't surprising. In fact, its a relief. I was concerned that we'd lose some of AltiVec's magic efficiency with the introduction of IBM's VMX equivalent. RC5 isn't very bandwidth intensive, I believe, so you're not seeing the benefits of the 6.4x improvement in bandwidth.</strong><hr></blockquote>
It's surprising because many people would assume that improvements would be made to VMX/AltiVec ... and those improvements would show up in a benchmark like the Distributed.net Client. However, when the MPC7450 first came out, it also showed linear scaling for RC5 performance vs the MPC7400...until a specific core for the MPC7450 was developed.
Linear scaling using the available MPC7450 RC5 core with an IBM PPC 970 isn't surprising to me in that case.
It's also worth noting that Distributed.net benchmarks are compiler specific, just like any other benchmark. For example, With GCC 2.95.2, the PPC-scalar OGR core benches around 14 mnodes/sec on my 2x1000 MHz G4. In contrast, the PPC-vector (AltiVec) core benches 21 mnodes/sec. Surprisingly, when I compiled the client and core with GCC 3.2 the scalar core trumped the vector core with a benchmark of 23 mnodes/sec.
I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.
<hr></blockquote>
Spec has often been said to be extremely bandwidth driven. Face it, the scores that the 970 is getting are there, in large part, because of the huge increase in bandwidth.
It's also why certain chips like large cache itaniums and power4s do so well in it. When you think about it, cache and bandwidth/latency are almost identical in effect when it comes to feeding data to the processor. hence the high bandwidth and high cache systems doing so well in spec.
For example, With GCC 2.95.2, the PPC-scalar OGR core benches around 14 mnodes/sec on my 2x1000 MHz G4. In contrast, the PPC-vector (AltiVec) core benches 21 mnodes/sec. Surprisingly, when I compiled the client and core with GCC 3.2 the scalar core trumped the vector core with a benchmark of 23 mnodes/sec.
Yes, gcc doesn't do a great job with Altivec or the PPC in general. 3.2 helps a lot.
Hopefully IBM's presence will motivate the gnu guys to update the gcc standard quickly on release on 970 (I imagine all they have to do is incorporate what Apple/IBM gives them, but this seems to have proven to be difficult for them in the past.)
To those who care, I'm working on planning to put together a highly optimized Altivec/VMX library for certain DSP tasks. Hand coding the Altivec, as I have been told (and seen), is still a way to get a great speed bonus. So there's still a long way for compilers to go, and an optimized compile can indeed make a huge difference.
G4 1,8 ghz : spec int (estimated) 551 at equal mhz the ppc 970 is 70 % faster
G4 1,8 ghz : spec fp estimated : 337 at equal mhz the ppc 970 is 312 % faster
So we have a chip that scale lineary for Altivec, and you know that altivec is the best SIMD unit in the world, that give you 70 % more power per mhz in integer, and more than three times for FP operations, add a better support of SMP and a very efficient FSB 900 mhz max compared to 166 mhz for the G4.
There is no reason to whin, Apple will be ALIVE. I don't know if we will see dual configurations, but if they exist they will smoke any MP in Intel world. (mac os X is better for MP than windows).
splinemodel, yeah, typically I wouldn't be surprised by compiler optimization improvements, but a 64% jump from GCC 2.95.2 to 3.2 (and 3.1 too) is just insane. It makes me wonder how much more optimized AltiVec could be under GCC if they put an effort into it. OGR should benefit from AltiVec yet the scalar core beats the vector core at this point.
Sixty-four percent! Hell, even a 10% performance jump is remarkable.
<strong>Moki, are you sure the future high-end is the 970 and not the G5?</strong><hr></blockquote>
Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
Apparently his Steveness wasn't pleased with their progress in terms of silicon and speed.
so we all know that SPEC marks aren't an indicator for real world - speeds... so what about dhrystone and whetstone - i think those will give enough info about the real speed of the 970
and please - steevy-baby .. give us our 970 in april :-) ... that'll fit perfectly into my plan to buy a new mac then.
<strong>I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.</strong><hr></blockquote>
Gets it from here:
[quote]The front-side bus electrically runs at 450-MHz, double-clocked to an effective rate of 900-MHz, generating a peak bandwidth of 7.2 Gbytes or 6.4 Gbytes/s of useable bandwidth after transaction overhead is taken into account, Sandon said.<hr></blockquote>
Aparts from that being remarkably efficient I believe it likely scales with the clock speed of the computer itself. So at 1.6 GHZ it will only be 800 MHz effective and at 2GHz it will be 1GHz effective. I haven't seen a technical paper yet though.
Someone said that this processor also was going into Sony Playstation 3. If this is the case the future of macgames might be real bright... I dont know but to me it would seem the step might not be so long. Another advantage of this might be that IBM would make larger quantitys of these chips bringing the price down. Or am I wrong
Comments
And finally, and this is speculation, I think that IBM under estimated the speed of these chips. If the chip has a 16-18 stage pipeline on 130nm process it should do 2GHz out of the gate. Maybe it's hotspots in the silicon that make it clock at 1.8... Consider a G4 with a 7 stage pipeline and made on 180nm can manage 1.25GHz...
<strong>Just because it supports up to 6.4GBps bandwidth doesn't mean the memory must max the bus. Apple should use the least expensive/best performing ratio memory available at the time. If this spring, that's probably PC2700 (what the Macs use now throttled) and that provides 2.7GBps. If a bus can fully deliver that, it would be an accomplishment in and of itself. If a new PowerMac with GPUL is introduced in the summer/fall then you may be looking at a 400MHz flavor of DDR-II. Either way it will impress. Also I hear the actual theoretical bandwidth of the processor is 7.2GBps, but IBM quotes 6.4 after bus overhead is factored in. And as a note, RapidIO is notorious for large overhead.
And finally, and this is speculation, I think that IBM under estimated the speed of these chips. If the chip has a 16-18 stage pipeline on 130nm process it should do 2GHz out of the gate. Maybe it's hotspots in the silicon that make it clock at 1.8... Consider a G4 with a 7 stage pipeline and made on 180nm can manage 1.25GHz...</strong><hr></blockquote>
I think I saw the pipeline for the CPU was 8 or 10 (saw that somewhere) but each unit such as fp int vmx etc each have thier own # pipelines stages.
Also for those still hung up on SPEC numbers
[code]
SPECint_base2000
=================
242 G4 800Mhz
259 G4 867Mhz
306 G4 1000Mhz
937 GPUL 1800Mhz
=================
SPECfp_base
=================
147 G4 800Mhz
153 G4 867Mhz
187 G4 1000Mhz
1051 GPUL 1800Mhz
=================
</pre><hr></blockquote>
Found the numbers for 800 867 and 1000 on c'st (I think that was the site) Oh and anyone have numbers for the 1250Ghz cpu's?
Dave
<strong>forgive me if this has been touched on already, but let's assume that the article is correct and we don't see this processor for another year or so. what happens in the mean time? faster g4s in the form of the g4+? will it scale up enough, at least two more times? or perhaps moto still has the g5 ready to make an intro the first of next year to be relegated to a lower end solution once the 970 comes out?</strong><hr></blockquote>
I'm wondering about this too. The PPC 970 sounds great, but 12-15 months is an awfully long time for Apple to keep tap dancing around system performance while saddled with the G4.
If Mot wasn't very motivated to improve the G4 for Apple to begin with, it would seem they'd now have even less motivation to provide Apple with something new over this next year. I suppose Apple might stick to Mot for iMacs and iBooks, and even TiBooks for awhile, with the 970s only going into top-of-the-line Power Macs and Xserves at first. But sooner or later it would seem Mot's on the way out.
Does anyone else see the 970 as indicitive of a bright future, but also see grim times until then?
<strong>I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.</strong><hr></blockquote>
I believe he extrapolated the 7.2 GBps theoretical maximum throughput from the 900 MHz clock of the FSB.
[quote]Originally posted by Programmer:
<strong>Linear scaling by clock rate isn't surprising. In fact, its a relief. I was concerned that we'd lose some of AltiVec's magic efficiency with the introduction of IBM's VMX equivalent. RC5 isn't very bandwidth intensive, I believe, so you're not seeing the benefits of the 6.4x improvement in bandwidth.</strong><hr></blockquote>
It's surprising because many people would assume that improvements would be made to VMX/AltiVec ... and those improvements would show up in a benchmark like the Distributed.net Client. However, when the MPC7450 first came out, it also showed linear scaling for RC5 performance vs the MPC7400...until a specific core for the MPC7450 was developed.
Linear scaling using the available MPC7450 RC5 core with an IBM PPC 970 isn't surprising to me in that case.
It's also worth noting that Distributed.net benchmarks are compiler specific, just like any other benchmark. For example, With GCC 2.95.2, the PPC-scalar OGR core benches around 14 mnodes/sec on my 2x1000 MHz G4. In contrast, the PPC-vector (AltiVec) core benches 21 mnodes/sec. Surprisingly, when I compiled the client and core with GCC 3.2 the scalar core trumped the vector core with a benchmark of 23 mnodes/sec.
[ 10-15-2002: Message edited by: Eugene ]</p>
[quote]
Originally posted by Programmer:
I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.
<hr></blockquote>
Spec has often been said to be extremely bandwidth driven. Face it, the scores that the 970 is getting are there, in large part, because of the huge increase in bandwidth.
It's also why certain chips like large cache itaniums and power4s do so well in it. When you think about it, cache and bandwidth/latency are almost identical in effect when it comes to feeding data to the processor. hence the high bandwidth and high cache systems doing so well in spec.
neye
SPECint_base2000
=================
242 G4 800Mhz
259 G4 867Mhz
306 G4 1000Mhz
937 GPUL 1800Mhz
=================
SPECfp_base
=================
147 G4 800Mhz
153 G4 867Mhz
187 G4 1000Mhz
1051 GPUL 1800Mhz
=================
like, WHOA. <img src="graemlins/surprised.gif" border="0" alt="[Surprised]" />
oooh i cant wait. im so giddy. like a little kid in a candy store.
[ 10-16-2002: Message edited by: Aris ]</p>
<strong>
For example, With GCC 2.95.2, the PPC-scalar OGR core benches around 14 mnodes/sec on my 2x1000 MHz G4. In contrast, the PPC-vector (AltiVec) core benches 21 mnodes/sec. Surprisingly, when I compiled the client and core with GCC 3.2 the scalar core trumped the vector core with a benchmark of 23 mnodes/sec.
[ 10-15-2002: Message edited by: Eugene ]</strong><hr></blockquote>
Yes, gcc doesn't do a great job with Altivec or the PPC in general. 3.2 helps a lot.
Hopefully IBM's presence will motivate the gnu guys to update the gcc standard quickly on release on 970 (I imagine all they have to do is incorporate what Apple/IBM gives them, but this seems to have proven to be difficult for them in the past.)
To those who care, I'm working on planning to put together a highly optimized Altivec/VMX library for certain DSP tasks. Hand coding the Altivec, as I have been told (and seen), is still a way to get a great speed bonus. So there's still a long way for compilers to go, and an optimized compile can indeed make a huge difference.
<strong>
SPECint_base2000
=================
242 G4 800Mhz
259 G4 867Mhz
306 G4 1000Mhz
937 GPUL 1800Mhz
=================
SPECfp_base
=================
147 G4 800Mhz
153 G4 867Mhz
187 G4 1000Mhz
1051 GPUL 1800Mhz
=================
like, WHOA. <img src="graemlins/surprised.gif" border="0" alt="[Surprised]" /> </strong><hr></blockquote>
let's do a small simulation :
G4 1,8 ghz : spec int (estimated) 551 at equal mhz the ppc 970 is 70 % faster
G4 1,8 ghz : spec fp estimated : 337 at equal mhz the ppc 970 is 312 % faster
So we have a chip that scale lineary for Altivec, and you know that altivec is the best SIMD unit in the world, that give you 70 % more power per mhz in integer, and more than three times for FP operations, add a better support of SMP and a very efficient FSB 900 mhz max compared to 166 mhz for the G4.
There is no reason to whin, Apple will be ALIVE. I don't know if we will see dual configurations, but if they exist they will smoke any MP in Intel world. (mac os X is better for MP than windows).
My personal feeling are :
Sixty-four percent! Hell, even a 10% performance jump is remarkable.
<strong>Moki, are you sure the future high-end is the 970 and not the G5?</strong><hr></blockquote>
Assuming you are talking about a "G5" from MOT -- don't hold your breath. I'm told Steve Jobs, after a particularly unproductive meeting with MOT representatives, told them to "Get the **** out of my office"
Apparently his Steveness wasn't pleased with their progress in terms of silicon and speed.
<strong>Apparently his Steveness wasn't pleased with their progress in terms of silicon and speed.
Yeah well, neither am I.
Bring on the Power Mac 64!
Barto
and please - steevy-baby .. give us our 970 in april :-) ... that'll fit perfectly into my plan to buy a new mac then.
<strong>I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.</strong><hr></blockquote>
Gets it from here:
[quote]The front-side bus electrically runs at 450-MHz, double-clocked to an effective rate of 900-MHz, generating a peak bandwidth of 7.2 Gbytes or 6.4 Gbytes/s of useable bandwidth after transaction overhead is taken into account, Sandon said.<hr></blockquote>
Aparts from that being remarkably efficient I believe it likely scales with the clock speed of the computer itself. So at 1.6 GHZ it will only be 800 MHz effective and at 2GHz it will be 1GHz effective. I haven't seen a technical paper yet though.
[ 10-16-2002: Message edited by: Telomar ]</p>