It's very possible that the current system controller is already designed to handle a 200 MHz FSB effectively. Currently the system controller can work with FSBs at both 133 and 166 MHz, and the DDR RAM in the Powermacs is more than fast enough to feed a 200 MHz FSB. I suspect it's merely an issue of dropping in a G4 with a faster FSB.
In fact I wouldn't be surprised if the current system controller could support a DDR FSB. For a part so expensive to design and implement, it seems like Apple would design it to have a life longer than a single G4 revision.</strong><hr></blockquote>
I would agree with you but one thing bothers me. If the FSB between CPU and main controller can support a 200MHz bus then what does this mean for memory support? a 133MHz bus uses now 266MHz DDR RAM and a 166MHz bus uses 333MHz RAM. Something tells me Apple is using a bus that synchronizes the RAM and bus speed 2:1 ratio.
<strong>the next iteration of PowerMac:s will not have fully integrated DDR-RAM since niether the current nor the next generation G4 processors support a doubble pumped system bus.
Motorola's proposed MPC7457-RM does as do IBM's PPC970.
Im just wontering why Apple jsut cant put both processors on separate busses to the U2-controller.. instead of sharing 1.2 GB/s, they's have 1.2 GB/s each to play with.. and the RAM-bus from U2 will be double pumped as usual.
did you hear from the next version of the G3 with 1Ghz+ - SMP support - multicore - SIMD unit and RapidIO ...? it's clearly on IBM's current PPC roadmap and will be shipped soon.
I would agree with you but one thing bothers me. If the FSB between CPU and main controller can support a 200MHz bus then what does this mean for memory support? a 133MHz bus uses now 266MHz DDR RAM and a 166MHz bus uses 333MHz RAM. Something tells me Apple is using a bus that synchronizes the RAM and bus speed 2:1 ratio.</strong><hr></blockquote>
the current RAM-Modules are PC2100 at 2*133=266Mhz and PC2700 at 2*166=333Mhz ... there are already PC3200-Ram Modules wich have 2*200=400Mhz
But they are not a JDEC standard. And have you checked the prices? I hope the bus is not synchronous and is asynchronous. But something tells me that it's matched.
<strong>DDR II is supposed to start appearing early next year, at 400 and 533MHz effective (100MHz and 133MHz quad pumped).
That would work.</strong><hr></blockquote>
It sure would. But not on the current motherboards. they would need to redesign the controller to support DDRII. And i think each slot has 200 pins versus the 184 of the DDRI standard.
New article at <a href="http://www.theinquirer.net/?article=6037"; target="_blank">The Inquirer</a> confirms much of the Architosh article on the "G5", also states that the erstwhile 7470 is now the 7457. Expect it 2Q03
<strong>New article at <a href="http://www.theinquirer.net/?article=6037"; target="_blank">The Inquirer</a> confirms much of the Architosh article on the "G5", also states that the erstwhile 7470 is now the 7457. Expect it 2Q03</strong><hr></blockquote>
That article is a lot of BS with no substantiated facts. The 7470 was a complete fabrication, that I suspect originated on these very boards and thus was forged into infamy.
<strong>Could they not use something like a 3:5 ratio? FSB:RAM 200:333? Or something like that, mebbe this is not possible, iDunno.</strong><hr></blockquote>
They could do this. It's not the first time this has been done. but the ball would be in Apple's court on this. I'm not exactly sure on the benefits of having a synchronous system/memory bus. I think if properly designed it should be OK.
It sure would. But not on the current motherboards. they would need to redesign the controller to support DDRII. And i think each slot has 200 pins versus the 184 of the DDRI standard.</strong><hr></blockquote>
Well, you know, you drop support for OS 9 and it's suddenly a bit easier to change up your hardware platform.
<strong>Well, you know, you drop support for OS 9 and it's suddenly a bit easier to change up your hardware platform.
</strong><hr></blockquote>
You don't know how true that is. Supporting legacy is very expensive, whether it is software or hardware.
The DDR chipset is probably designed for a fixed ratio between the buses just to simplify the internal handshaking between the different interfaces. I doubt that the existing chipset has much more capability than we're aware of, but I would guess that internally it is designed in a modular fashion so that they can quickly whip out new designs with certain modules replaced... i.e. the MPX interface removed and the GPUL bus interface added. This makes it easier to create new versions, and it also improves compatibility from generation to generation. It is not in Apple's interest to ship a chipset that has a bunch of capabilities that will never be used (and certainly they wouldn't want to encourage upgrades!).
Comments
<strong>
It's very possible that the current system controller is already designed to handle a 200 MHz FSB effectively. Currently the system controller can work with FSBs at both 133 and 166 MHz, and the DDR RAM in the Powermacs is more than fast enough to feed a 200 MHz FSB. I suspect it's merely an issue of dropping in a G4 with a faster FSB.
In fact I wouldn't be surprised if the current system controller could support a DDR FSB. For a part so expensive to design and implement, it seems like Apple would design it to have a life longer than a single G4 revision.</strong><hr></blockquote>
I would agree with you but one thing bothers me. If the FSB between CPU and main controller can support a 200MHz bus then what does this mean for memory support? a 133MHz bus uses now 266MHz DDR RAM and a 166MHz bus uses 333MHz RAM. Something tells me Apple is using a bus that synchronizes the RAM and bus speed 2:1 ratio.
<strong>the next iteration of PowerMac:s will not have fully integrated DDR-RAM since niether the current nor the next generation G4 processors support a doubble pumped system bus.
Motorola's proposed MPC7457-RM does as do IBM's PPC970.
Im just wontering why Apple jsut cant put both processors on separate busses to the U2-controller.. instead of sharing 1.2 GB/s, they's have 1.2 GB/s each to play with.. and the RAM-bus from U2 will be double pumped as usual.
[ 10-31-2002: Message edited by: Henriok ]</strong><hr></blockquote>
did you hear from the next version of the G3 with 1Ghz+ - SMP support - multicore - SIMD unit and RapidIO ...? it's clearly on IBM's current PPC roadmap and will be shipped soon.
<strong>
I would agree with you but one thing bothers me. If the FSB between CPU and main controller can support a 200MHz bus then what does this mean for memory support? a 133MHz bus uses now 266MHz DDR RAM and a 166MHz bus uses 333MHz RAM. Something tells me Apple is using a bus that synchronizes the RAM and bus speed 2:1 ratio.</strong><hr></blockquote>
the current RAM-Modules are PC2100 at 2*133=266Mhz and PC2700 at 2*166=333Mhz ... there are already PC3200-Ram Modules wich have 2*200=400Mhz
greets,
krassy
That would work.
<strong>DDR II is supposed to start appearing early next year, at 400 and 533MHz effective (100MHz and 133MHz quad pumped).
That would work.</strong><hr></blockquote>
It sure would. But not on the current motherboards. they would need to redesign the controller to support DDRII. And i think each slot has 200 pins versus the 184 of the DDRI standard.
...and for Mac users...? Place yer bets, folks. How about 2005?
Lemon Bon Bon
<strong>New article at <a href="http://www.theinquirer.net/?article=6037"; target="_blank">The Inquirer</a> confirms much of the Architosh article on the "G5", also states that the erstwhile 7470 is now the 7457. Expect it 2Q03</strong><hr></blockquote>
That article is a lot of BS with no substantiated facts. The 7470 was a complete fabrication, that I suspect originated on these very boards and thus was forged into infamy.
Could they not use something like a 3:5 ratio? FSB:RAM 200:333? Or something like that, mebbe this is not possible, iDunno.
<strong>Could they not use something like a 3:5 ratio? FSB:RAM 200:333? Or something like that, mebbe this is not possible, iDunno.</strong><hr></blockquote>
They could do this. It's not the first time this has been done. but the ball would be in Apple's court on this. I'm not exactly sure on the benefits of having a synchronous system/memory bus. I think if properly designed it should be OK.
<strong>
It sure would. But not on the current motherboards. they would need to redesign the controller to support DDRII. And i think each slot has 200 pins versus the 184 of the DDRI standard.</strong><hr></blockquote>
Well, you know, you drop support for OS 9 and it's suddenly a bit easier to change up your hardware platform.
[ 11-04-2002: Message edited by: Amorph ]</p>
<strong>Well, you know, you drop support for OS 9 and it's suddenly a bit easier to change up your hardware platform.
</strong><hr></blockquote>
You don't know how true that is. Supporting legacy is very expensive, whether it is software or hardware.
The DDR chipset is probably designed for a fixed ratio between the buses just to simplify the internal handshaking between the different interfaces. I doubt that the existing chipset has much more capability than we're aware of, but I would guess that internally it is designed in a modular fashion so that they can quickly whip out new designs with certain modules replaced... i.e. the MPX interface removed and the GPUL bus interface added. This makes it easier to create new versions, and it also improves compatibility from generation to generation. It is not in Apple's interest to ship a chipset that has a bunch of capabilities that will never be used (and certainly they wouldn't want to encourage upgrades!).