I don't think any one here seriously thinks that this new Power 4+ processor will end up in an Apple branded product. I do believe the salient point is this is a dual core processor currently being manufactured on a 0.13µ processor.
I think all of IBM's recent G3 processors (the CX, CXe, FX) use coreconnect for internal on die connections. Not sure about the 970 or Power4, but I wouldn't be surprised. RapidIO may be slated for a future 7XX series PowerPC. I can see one with VMX and RapidIO servicing the iBook and iMac lines.
<strong>I think all of IBM's recent G3 processors (the CX, CXe, FX) use coreconnect for internal on die connections. Not sure about the 970 or Power4, but I wouldn't be surprised. RapidIO may be slated for a future 7XX series PowerPC. I can see one with VMX and RapidIO servicing the iBook and iMac lines.</strong><hr></blockquote>
Would an n-way Crossbar Coreconnect be the same? If so, check off one more tech already developed.
You think a multcore superscalar processor would be used in a G3. I was thinking the next generation would be high end, especially if the pipelines were extended slightly.
Oh, I forgot, I was thinking the next generation PowerPC on the roadmap wouldn't be in the 7XX series, maybe a 8XX series.
<strong>The 601 implemented some extra instructions so a compiler could be made available, but I doubt it implemented the entire POWER instruction set (which would be Amazon+PPC)</strong><hr></blockquote>
Hmm. Perhaps it had traps/exceptions or something to allow the full POWER instruction set to work transparently to the user. I couldn't say. I just remember rooms full of IBM RS6000s with 601's inside. I never heard complaints 'xlc says no POWER instructions available' or anything like that. Shrug.
Comments
Let's see, <a href="http://www-3.ibm.com/chips/products/powerpc/rdmap/"; target="_blank">IBM's roadmap</a> for the PowerPC lists the next generation as having;
- 1+ GHz
- Multicore Superscalar
- SMP Capable
- Integrated SIMID Engine
- Rapid I/O
- n-way Crossbar Coreconnect
- Low-k dielectric 0.13 - 0.10µm
IBM has been working on SIMID, see the 970.IBM has been manufacturing on a 0.13µm process, see the G3 & now the Power4+
IBM has SMP capabilities developed, Powrer4, etc.
That leaves Rapid I/O and n-way Crossbar Coreconnect. Wonder how much time and resources they have been spending on this???
Any guesses when this processor will appear??
[ 11-13-2002: Message edited by: rickag ]</p>
<strong>I think all of IBM's recent G3 processors (the CX, CXe, FX) use coreconnect for internal on die connections. Not sure about the 970 or Power4, but I wouldn't be surprised. RapidIO may be slated for a future 7XX series PowerPC. I can see one with VMX and RapidIO servicing the iBook and iMac lines.</strong><hr></blockquote>
Would an n-way Crossbar Coreconnect be the same? If so, check off one more tech already developed.
You think a multcore superscalar processor would be used in a G3. I was thinking the next generation would be high end, especially if the pipelines were extended slightly.
Oh, I forgot, I was thinking the next generation PowerPC on the roadmap wouldn't be in the 7XX series, maybe a 8XX series.
[ 11-13-2002: Message edited by: rickag ]</p>
<strong>The 601 implemented some extra instructions so a compiler could be made available, but I doubt it implemented the entire POWER instruction set (which would be Amazon+PPC)</strong><hr></blockquote>
Hmm. Perhaps it had traps/exceptions or something to allow the full POWER instruction set to work transparently to the user. I couldn't say. I just remember rooms full of IBM RS6000s with 601's inside. I never heard complaints 'xlc says no POWER instructions available' or anything like that. Shrug.
<strong>Crossbar CoreConnect is not the same thing as CoreConnect; all the current embedded PowerPC SoCs are based on buses.</strong><hr></blockquote>
Ok, add n-way Crossbar CoreConnect back to tech not yet implemented along with Rapid I/O..
Still, any guesses/inside information when this chip appears.