This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.
You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
The PPC 970 chip and derived are the future of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.
You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
The PPC 970 chip and derived are the future of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache
And
Quote:
Originally posted by Programmer
.
.
.
SMT
on-chip memory controller
system-on-chip I/O features
.
.
.
One point that I remember is that the PPC would be the area for the cutting edge stuff, and the things that had been perfected there would then migrate to the POWER series. I quote "The POWER series will always lag the PPC series because they IBM will never ship someting that is not mature in hte POWER series." NOTE that all of the above mentioned improvements are to be found in the POWER5, OK maybe not S-O-C I/O features, but the rest I'm pretty sure of. Maybe it is the other way around the PPC will inherit from the POWER series.
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.
True but those server features do not detract from its usefullness to Apple. I would have to think at some point that adding the little bit extra to Power5 that Apple needs for its machines would in the end be a win for everybody.
Quote:
You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
This I agree with, but on the other hand it shouldn't be to difficult to derive a new PPC chip from Power5 just like they did for the 970 and Power4. It makes more sense from an engineering point of view than maintaining an old architecture. Not that Power4 / 970xx is old just that development effort would make more sense on hardware expected to be around for a few years.
I think you also underestimate performance improvements. From the system point of view I can see OS/X making real good use of Power5 derived hardware.
Quote:
The PPC 970 chip and derived are the future of Apple.
From the day in debuted I have been convinced that that is not the case. I see the 970 series as a stop gap measure that Apple pursued due to basically being desperate. If IBM had long term intentions with respect to the 970 series they would have made some design decisions that would make it usefull and saleable to markets outside of Apple.
Quote:
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache
True all of these improvements can help but then agian you can get the same results by tacking a Vector unit onto a Power5 and optimising the chip for 90nm processing. In the end does it really make sense to back port hardware you already have working in Power5, especially considering that a 90nm Power5 derived core will untimately still be smaller than the dual core hardware Intel and AMD will be shipping in large quanities next year. That Power5 derived core would only have to be optimized/altered in a few places for desktop use.
That is one point of view. The reality is that IBM has so many projects going on right now, with respect to Power and PPC, that it is hard to tell what Apple will get in the future. If Cell or the MS driven hardware is at all successfull and delivers on promise we could have some surprises from Apple. The reality is Apple needs hardware that supports multithreading/multiprocessing cheaply. An approach that gets lots of core on chip is likely to be the winnning approach.
What's this? We agree? Do I hear hell freezing over?
Well not exactly as I consider adding instruction that do not impact the current ISA fair game. I fully understand that there is much that can be done within the current instruction set for Vector operations. Everyone seems to agree on that as frankly not much has changed with AltVec in a long time. The point is that I also see enhanced istructions as being an important step forward also.
Quote:
First of all, what do you mean by "a seperate execution unit"? Right now AltiVec is a pair of seperate execution units -- seperate from the load/store, integer, and floating point execution units. I suspect you mean as a seperate core, like Cell is rumoured to be.
That is exactly what I was thinking about and my lack of preciseness is regretted. The point is that if Cell becomes a run away succcess (Personally I highly doubt that) Apple may be forced to make changes. One of those changes would be to adopt Chips with many CORES, which is difficult to do if everyone of them has a big vector unit attached.
Quote:
In this case I agree but they don't have to be mutually exclusive: the presence of specialized vector cores doesn't obviate the need for vector execution units in the general purpose core any more than specialized floating point cores would obviate the need in the general purpose core.
In a world of quick and light cores, the current arraingement with AltVec would have to disappear. If you need 4 to 8 real cores on a chip you won't be able to do that with an extra execution unit on each one.
Quote:
VMX will be supported, mark my words.
Yes it will probally be supported mostly due to Appl having so much code invested in it. The problem is does this become a ball and chain around the flagship product? Frankly I don't know alot about the MS or Sony approaches other than the heavy reliance upon apparently many cores. If however either company can start to deliver a low cost truely high performance workstation to the market Apple will have to take notice. Imagine a workstation with 3 to 8 PPC cores plus whatever vector facilites they decide to implement, sound earth shaking to me.
[B]True but those server features do not detract from its usefullness to Apple. I would have to think at some point that adding the little bit extra to Power5 that Apple needs for its machines would in the end be a win for everybody.
And they could very well do it, in fact I think they will include VMX in some future chip. I don't buy the argument that VMX is not useful in servers. They must see that Apple puts it to good use and there are some areas in computational servers (as opposed to file/print servers) where VMX would help IBM (look at what Altivec does for BLAST for instance, biotechnology is an area IBM are investing in heavily).
I think it is a matter of time. There seemed to be a thawing in IBM's attitude to VMX a few years ago. Power 4 was a massive 5 year project started before the first release of the G4 series of designs. Power 5 was started well before Power 4 was finished so it might have had many elements of the design nailed down before the change of attitude to VMX. Power 6 might have started late enough to have it included in the design.
the discussion of adding altivec or not is completely bogus.
soon we will see chips with a billion transistors. altivec is composed of a couple of million transistors. the question right now is how to exploit the performance out of so many transistors. answers to this include SMT, multiple cores, IMC, SIMD units, cache, super scalarity and OOOE.
second point. the rumored PPC 970MP looks a lot like Power4. It's a dual core chip, with more or less identical cores to Power4. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size and process tech.
a proposed Power5 variant will be very very close to Power5 too. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size, process tech and possibly some of the self-healing redundancy stuff.
about altivec 2. i heard quite some whining that altivec does not support double precision fps. while it is right that altivec is a very solid design, saying there is no room for improvement in the ISA is dumb. as long as a improved altivec 2 is compatible with altivec there is no problem at all. the fragmentation of instruction sets has been a reality for software developers forever. there is no stability. in the mac space examples for this are 68k->PPC and G3->G4. as a software developer you are accustomed to change. In Java with every version new capabilties are added and other are being deprecated and ultimately become unsupported.
of course optimizations in implementation will improve performance, but this cannot be the sole way of improvement.
as programmer pointed out earlier autovectorization is coming to gcc and Apple ships several libraries with common math functions, etc with OS X. this means that the programmer is liberated from knowing the instruction set. as long as the semantics are defined those libraries or the compiler will generate quite good code.
i want to open another topic. we are moving to multiple cores. how are we going to feed the beasts? currently one processor sits on one bus. i suppose performance will degrade noticeably when multiple cores share a bus. isn't the time ripe for NUMA in a pc?
While I don't totally disagree with you I do have some comments.
Quote:
Originally posted by cocoa tree
hi there,
the discussion of adding altivec or not is completely bogus.
soon we will see chips with a billion transistors. altivec is composed of a couple of million transistors. the question right now is how to exploit the performance out of so many transistors. answers to this include SMT, multiple cores, IMC, SIMD units, cache, super scalarity and OOOE.
second point. the rumored PPC 970MP looks a lot like Power4. It's a dual core chip, with more or less identical cores to Power4. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size and process tech.
a proposed Power5 variant will be very very close to Power5 too. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size, process tech and possibly some of the self-healing redundancy stuff.
As you mentioned above we are coming into an age where we will have a huge number of transistors available on a die. Why bother with a version of Power 5 that deletes SMP, hypervisor or anything else that might be usefull on the desk top? As to SMP it is glaringly obvious where the industry is going there, I suspect in a couple of years it will be difficult to even buy a processor with less than 2 cores. The rest of Power 5 is modular enough that a new memory controller should not be an issue if needed. Even that I question as the current Power5 memory arrangement is implementable on a desktop PC.
Quote:
about altivec 2. i heard quite some whining that altivec does not support double precision fps. while it is right that altivec is a very solid design, saying there is no room for improvement in the ISA is dumb. as long as a improved altivec 2 is compatible with altivec there is no problem at all. the fragmentation of instruction sets has been a reality for software developers forever. there is no stability. in the mac space examples for this are 68k->PPC and G3->G4. as a software developer you are accustomed to change. In Java with every version new capabilties are added and other are being deprecated and ultimately become unsupported.
AltVec and a redevelopment into AltVec2 should not be a problem as you pointed out. For those not interested or not able to take advantage of new performance features in AltVec2, they can just code for AltVec. There is much that can be done to improve AltVec, both for the general case and specific applications.
As to instruction set expansions what I'd love to see is an on board logic array that would allow one to build and execute application specific logic. One of my Linux mags has an interesting article on this, it would be neat to have such an array available as another core on the die.
Quote:
of course optimizations in implementation will improve performance, but this cannot be the sole way of improvement.
as programmer pointed out earlier autovectorization is coming to gcc and Apple ships several libraries with common math functions, etc with OS X. this means that the programmer is liberated from knowing the instruction set. as long as the semantics are defined those libraries or the compiler will generate quite good code.
While some of the libraries are excellent the idea that a compiler will generate good vector code is still to be proven. Ultimate exploitation of this hardware requires manual intervention at this time.
Quote:
i want to open another topic. we are moving to multiple cores. how are we going to feed the beasts? currently one processor sits on one bus. i suppose performance will degrade noticeably when multiple cores share a bus. isn't the time ripe for NUMA in a pc?
thanks for your comments.
bye cocoa tree
As to on chip SMP you have a good question, I suspect that FOR MOST APPLICATIONS it will be a win. You will take a hit though if both threads are nearly saturating the memory bus. The question is how often does this happen, like all things PC related this is really user related.
As can be seen in the AMD world, NUMA does have its advantages. They will soon have dual core chips widely available so answers will soon be there for the asking. The biggest difference with AMD hardware is the onboard memory controller of course. I suspect that Apple/IBM will either have to move to this soon especially if the current FSB starts to have problems scaling. In other words if they have to go to a 3 to 1 bus at 3GHz I think we will start to see pressure for an integrated memory controller. We might also see this presure if they put a G4 derived processor with an integrated memory controller into a portable and it shows considerable improvements.
Ultimately Power5 seems to have solutions to some of the problems discussed. The primary one being the on board memory interface.
What I meant, is that IBM has two lines of processor the power line and the PPC line. Apple will never use the powerline in his desktop computers.
That do not mean, that the PPC line will not benefit from some improvements coming from the power line, like SMT and multicore, nor the powerline will not benefit from improvements coming from the PPC line like altivec.
Must be tough to sit there and watch the rest of us project (geuss) where the porcessor line is going!!!
In any event I don't think the wait is all that long. Another round of 970 derived chips and then on to the next generation is my geuss. This new hardware could be avialable soon in the new year.
Actually of late my interest has been directed more at the portable low power market. Some of the noise coming from IBM seems to indicate a huge jump in capability soon with respect to the portable market. That noise however does not specifically say the portable chip is ready but hey we can hope. Hoping is more than I was doing even a couple weeks ago.
Dave
Quote:
Originally posted by Programmer
<gurgle>
Sorry, I have to drop out of this discussion. NDAs are a bitch.
Obviously you can't talk about what you know, but which post here would a wise man ignore?
I'm fairly lucky with what I'm doing now. Totally unrelated to anything discussed here. In fact just the mention of Apple products causes people to ask if they are still in business around here.
Came across something interesting while combing through the change log for the latest Linux kernel. I also posted this snip over on Ars.
Quote:
[PATCH] Create cpu_sibling_map for PPC64
\t
\tIn light of some proposed changes in the sched_domains code, I coded up
\tthis little ditty that simply creates and populates a cpu_sibling_map for
\tPPC64 machines. The patch just checks the CPU flags to determine if the
\tCPU supports SMT (aka Hyper-Threading aka Multi-Threading aka ...) and
\tfills in a mask of the siblings for each CPU in the system. This should
\tallow us to build sched_domains for PPC64 with generic code in
\tkernel/sched.c for the SMT systems. SMT is becoming more popular and is
\tturning up in more and more architectures. I don't think it will be too
\tlong until this feature is supported by most arches...
Now that last sentence seems to indicate that SMT is not far off for desktop processors. It is unknown if the individual actually knows what the future is about to deliver or if he is just geussing about future directions.
It does give me a little hope that the future with SMT is not that far away.
Now the question that comes to mind is this a future with Power5 derived hardware or is it a future with SMT bolted onto a 970. One also has to consider is Power5 just Power4 with SMT bolted on. Yeah I know there is more to it than that but I hope everyone gets the general idea. Personally I think the Power5 derived core would be the path of least resistance.
Came across something interesting while combing through the change log for the latest Linux kernel. I also posted this snip over on Ars.
Now that last sentence seems to indicate that SMT is not far off for desktop processors. It is unknown if the individual actually knows what the future is about to deliver or if he is just geussing about future directions.
It does give me a little hope that the future with SMT is not that far away.
Now the question that comes to mind is this a future with Power5 derived hardware or is it a future with SMT bolted onto a 970. One also has to consider is Power5 just Power4 with SMT bolted on. Yeah I know there is more to it than that but I hope everyone gets the general idea. Personally I think the Power5 derived core would be the path of least resistance.
Thanks
Dave
My take on this is that he is talking about the 970 and the like. It has been my experience that when people are talking about the POWER series that is how they refer to it POWER. When people are referring to the 970 and the like they say PPC the 64 part just nails it as being 970 like, as opposed to other versions of the PPC that are not 64. Yes it does look like SMT is coming soon like maybe in the March revision time frame. We all knew that clock rate increases at least at the 90 level is expensive, in many ways, to do. So the promise to Apple is performance increases, some equate that only with clock rate others know that there are many different technologies that can come to the PPC 9XX processors and give them significant performance increases and never need to increase the clock rate, not saying that IBM cannot increase the clock rate, but I would rather have these technologies rather than have another 500MHz clock raate increase. I tend to think that these other technologies like SMT, more cores, on die memory controller, rapid IO, improved Altivec, and the like add up to more than 500MHZ performance wise.
And why not? If you hide the POWER4 box under a desk, who would know the difference? My point is that what most people call a "Mac" is not the hardware but the user experience one gets from using the OSX software. If you run LINUX on an Apple G5 machine, is that a Mac? I say absolutely not because the user experience is completely different. So, by my way of thinking, a POWER4/POWER5 Mac is very feasible because all it takes is porting OSX to any of the fine IBM POWER5 boxes. All Apple has to do is refrain from suing whoever is doing the porting .
Obviously you can't talk about what you know, but which post here would a wise man ignore?
Nice try.
Quote:
I'm fairly lucky with what I'm doing now. Totally unrelated to anything discussed here. In fact just the mention of Apple products causes people to ask if they are still in business around here.
Normally I post here freely because I don't know anything about Apple's plans either.
Normally I post here freely because I don't know anything about Apple's plans either.
Niether do I so post away I will!
Lots of news coming out lately. Now IBM has indicated that they are moving Hypervisor support or something similar into one of the next PPC chips. If SMT support is there also then I'd have to say it is pretty clear that the next or 2nd to the next PPC is in fact derived from Power5.
Now the question is how soon can Apple and IBM actually deliver working systems? I'm still thinking that something this big will probally wait for WWDC though a big boost at MWSF would be nice.
So, by my way of thinking, a POWER4/POWER5 Mac is very feasible because all it takes is porting OSX to any of the fine IBM POWER5 boxes. All Apple has to do is refrain from suing whoever is doing the porting .
Right, so you go ahead and port it then. I'll just wait over here.
Comments
Originally posted by Powerdoc
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.
You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
The PPC 970 chip and derived are the future of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache
.
.
.
SMT
on-chip memory controller
system-on-chip I/O features
.
.
.
Originally posted by Powerdoc
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.
You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
The PPC 970 chip and derived are the future of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache
And
Originally posted by Programmer
.
.
.
SMT
on-chip memory controller
system-on-chip I/O features
.
.
.
One point that I remember is that the PPC would be the area for the cutting edge stuff, and the things that had been perfected there would then migrate to the POWER series. I quote "The POWER series will always lag the PPC series because they IBM will never ship someting that is not mature in hte POWER series." NOTE that all of the above mentioned improvements are to be found in the POWER5, OK maybe not S-O-C I/O features, but the rest I'm pretty sure of. Maybe it is the other way around the PPC will inherit from the POWER series.
Originally posted by Powerdoc
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.
True but those server features do not detract from its usefullness to Apple. I would have to think at some point that adding the little bit extra to Power5 that Apple needs for its machines would in the end be a win for everybody.
You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
This I agree with, but on the other hand it shouldn't be to difficult to derive a new PPC chip from Power5 just like they did for the 970 and Power4. It makes more sense from an engineering point of view than maintaining an old architecture. Not that Power4 / 970xx is old just that development effort would make more sense on hardware expected to be around for a few years.
I think you also underestimate performance improvements. From the system point of view I can see OS/X making real good use of Power5 derived hardware.
The PPC 970 chip and derived are the future of Apple.
From the day in debuted I have been convinced that that is not the case. I see the 970 series as a stop gap measure that Apple pursued due to basically being desperate. If IBM had long term intentions with respect to the 970 series they would have made some design decisions that would make it usefull and saleable to markets outside of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache
True all of these improvements can help but then agian you can get the same results by tacking a Vector unit onto a Power5 and optimising the chip for 90nm processing. In the end does it really make sense to back port hardware you already have working in Power5, especially considering that a 90nm Power5 derived core will untimately still be smaller than the dual core hardware Intel and AMD will be shipping in large quanities next year. That Power5 derived core would only have to be optimized/altered in a few places for desktop use.
That is one point of view. The reality is that IBM has so many projects going on right now, with respect to Power and PPC, that it is hard to tell what Apple will get in the future. If Cell or the MS driven hardware is at all successfull and delivers on promise we could have some surprises from Apple. The reality is Apple needs hardware that supports multithreading/multiprocessing cheaply. An approach that gets lots of core on chip is likely to be the winnning approach.
Dave
Originally posted by Programmer
What's this? We agree? Do I hear hell freezing over?
Well not exactly as I consider adding instruction that do not impact the current ISA fair game. I fully understand that there is much that can be done within the current instruction set for Vector operations. Everyone seems to agree on that as frankly not much has changed with AltVec in a long time. The point is that I also see enhanced istructions as being an important step forward also.
First of all, what do you mean by "a seperate execution unit"? Right now AltiVec is a pair of seperate execution units -- seperate from the load/store, integer, and floating point execution units. I suspect you mean as a seperate core, like Cell is rumoured to be.
That is exactly what I was thinking about and my lack of preciseness is regretted. The point is that if Cell becomes a run away succcess (Personally I highly doubt that) Apple may be forced to make changes. One of those changes would be to adopt Chips with many CORES, which is difficult to do if everyone of them has a big vector unit attached.
In this case I agree but they don't have to be mutually exclusive: the presence of specialized vector cores doesn't obviate the need for vector execution units in the general purpose core any more than specialized floating point cores would obviate the need in the general purpose core.
In a world of quick and light cores, the current arraingement with AltVec would have to disappear. If you need 4 to 8 real cores on a chip you won't be able to do that with an extra execution unit on each one.
VMX will be supported, mark my words.
Yes it will probally be supported mostly due to Appl having so much code invested in it. The problem is does this become a ball and chain around the flagship product? Frankly I don't know alot about the MS or Sony approaches other than the heavy reliance upon apparently many cores. If however either company can start to deliver a low cost truely high performance workstation to the market Apple will have to take notice. Imagine a workstation with 3 to 8 PPC cores plus whatever vector facilites they decide to implement, sound earth shaking to me.
Dave
Originally posted by wizard69
[B]True but those server features do not detract from its usefullness to Apple. I would have to think at some point that adding the little bit extra to Power5 that Apple needs for its machines would in the end be a win for everybody.
And they could very well do it, in fact I think they will include VMX in some future chip. I don't buy the argument that VMX is not useful in servers. They must see that Apple puts it to good use and there are some areas in computational servers (as opposed to file/print servers) where VMX would help IBM (look at what Altivec does for BLAST for instance, biotechnology is an area IBM are investing in heavily).
I think it is a matter of time. There seemed to be a thawing in IBM's attitude to VMX a few years ago. Power 4 was a massive 5 year project started before the first release of the G4 series of designs. Power 5 was started well before Power 4 was finished so it might have had many elements of the design nailed down before the change of attitude to VMX. Power 6 might have started late enough to have it included in the design.
the discussion of adding altivec or not is completely bogus.
soon we will see chips with a billion transistors. altivec is composed of a couple of million transistors. the question right now is how to exploit the performance out of so many transistors. answers to this include SMT, multiple cores, IMC, SIMD units, cache, super scalarity and OOOE.
second point. the rumored PPC 970MP looks a lot like Power4. It's a dual core chip, with more or less identical cores to Power4. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size and process tech.
a proposed Power5 variant will be very very close to Power5 too. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size, process tech and possibly some of the self-healing redundancy stuff.
about altivec 2. i heard quite some whining that altivec does not support double precision fps. while it is right that altivec is a very solid design, saying there is no room for improvement in the ISA is dumb. as long as a improved altivec 2 is compatible with altivec there is no problem at all. the fragmentation of instruction sets has been a reality for software developers forever. there is no stability. in the mac space examples for this are 68k->PPC and G3->G4. as a software developer you are accustomed to change. In Java with every version new capabilties are added and other are being deprecated and ultimately become unsupported.
of course optimizations in implementation will improve performance, but this cannot be the sole way of improvement.
as programmer pointed out earlier autovectorization is coming to gcc and Apple ships several libraries with common math functions, etc with OS X. this means that the programmer is liberated from knowing the instruction set. as long as the semantics are defined those libraries or the compiler will generate quite good code.
i want to open another topic. we are moving to multiple cores. how are we going to feed the beasts? currently one processor sits on one bus. i suppose performance will degrade noticeably when multiple cores share a bus. isn't the time ripe for NUMA in a pc?
thanks for your comments.
bye cocoa tree
While I don't totally disagree with you I do have some comments.
Originally posted by cocoa tree
hi there,
the discussion of adding altivec or not is completely bogus.
soon we will see chips with a billion transistors. altivec is composed of a couple of million transistors. the question right now is how to exploit the performance out of so many transistors. answers to this include SMT, multiple cores, IMC, SIMD units, cache, super scalarity and OOOE.
second point. the rumored PPC 970MP looks a lot like Power4. It's a dual core chip, with more or less identical cores to Power4. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size and process tech.
a proposed Power5 variant will be very very close to Power5 too. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size, process tech and possibly some of the self-healing redundancy stuff.
As you mentioned above we are coming into an age where we will have a huge number of transistors available on a die. Why bother with a version of Power 5 that deletes SMP, hypervisor or anything else that might be usefull on the desk top? As to SMP it is glaringly obvious where the industry is going there, I suspect in a couple of years it will be difficult to even buy a processor with less than 2 cores. The rest of Power 5 is modular enough that a new memory controller should not be an issue if needed. Even that I question as the current Power5 memory arrangement is implementable on a desktop PC.
about altivec 2. i heard quite some whining that altivec does not support double precision fps. while it is right that altivec is a very solid design, saying there is no room for improvement in the ISA is dumb. as long as a improved altivec 2 is compatible with altivec there is no problem at all. the fragmentation of instruction sets has been a reality for software developers forever. there is no stability. in the mac space examples for this are 68k->PPC and G3->G4. as a software developer you are accustomed to change. In Java with every version new capabilties are added and other are being deprecated and ultimately become unsupported.
AltVec and a redevelopment into AltVec2 should not be a problem as you pointed out. For those not interested or not able to take advantage of new performance features in AltVec2, they can just code for AltVec. There is much that can be done to improve AltVec, both for the general case and specific applications.
As to instruction set expansions what I'd love to see is an on board logic array that would allow one to build and execute application specific logic. One of my Linux mags has an interesting article on this, it would be neat to have such an array available as another core on the die.
of course optimizations in implementation will improve performance, but this cannot be the sole way of improvement.
as programmer pointed out earlier autovectorization is coming to gcc and Apple ships several libraries with common math functions, etc with OS X. this means that the programmer is liberated from knowing the instruction set. as long as the semantics are defined those libraries or the compiler will generate quite good code.
While some of the libraries are excellent the idea that a compiler will generate good vector code is still to be proven. Ultimate exploitation of this hardware requires manual intervention at this time.
i want to open another topic. we are moving to multiple cores. how are we going to feed the beasts? currently one processor sits on one bus. i suppose performance will degrade noticeably when multiple cores share a bus. isn't the time ripe for NUMA in a pc?
thanks for your comments.
bye cocoa tree
As to on chip SMP you have a good question, I suspect that FOR MOST APPLICATIONS it will be a win. You will take a hit though if both threads are nearly saturating the memory bus. The question is how often does this happen, like all things PC related this is really user related.
As can be seen in the AMD world, NUMA does have its advantages. They will soon have dual core chips widely available so answers will soon be there for the asking. The biggest difference with AMD hardware is the onboard memory controller of course. I suspect that Apple/IBM will either have to move to this soon especially if the current FSB starts to have problems scaling. In other words if they have to go to a 3 to 1 bus at 3GHz I think we will start to see pressure for an integrated memory controller. We might also see this presure if they put a G4 derived processor with an integrated memory controller into a portable and it shows considerable improvements.
Ultimately Power5 seems to have solutions to some of the problems discussed. The primary one being the on board memory interface.
Dave
Sorry, I have to drop out of this discussion. NDAs are a bitch.
What I meant, is that IBM has two lines of processor the power line and the PPC line. Apple will never use the powerline in his desktop computers.
That do not mean, that the PPC line will not benefit from some improvements coming from the power line, like SMT and multicore, nor the powerline will not benefit from improvements coming from the PPC line like altivec.
In any event I don't think the wait is all that long. Another round of 970 derived chips and then on to the next generation is my geuss. This new hardware could be avialable soon in the new year.
Actually of late my interest has been directed more at the portable low power market. Some of the noise coming from IBM seems to indicate a huge jump in capability soon with respect to the portable market. That noise however does not specifically say the portable chip is ready but hey we can hope. Hoping is more than I was doing even a couple weeks ago.
Dave
Originally posted by Programmer
<gurgle>
Sorry, I have to drop out of this discussion. NDAs are a bitch.
Originally posted by wizard69
Must be tough to sit there and watch the rest of us project (guess) where the porcessor line is going!!!
You have no idea.
I'm fairly lucky with what I'm doing now. Totally unrelated to anything discussed here. In fact just the mention of Apple products causes people to ask if they are still in business around here.
Thanks
dave
Originally posted by Programmer
You have no idea.
Came across something interesting while combing through the change log for the latest Linux kernel. I also posted this snip over on Ars.
[PATCH] Create cpu_sibling_map for PPC64
\t
\tIn light of some proposed changes in the sched_domains code, I coded up
\tthis little ditty that simply creates and populates a cpu_sibling_map for
\tPPC64 machines. The patch just checks the CPU flags to determine if the
\tCPU supports SMT (aka Hyper-Threading aka Multi-Threading aka ...) and
\tfills in a mask of the siblings for each CPU in the system. This should
\tallow us to build sched_domains for PPC64 with generic code in
\tkernel/sched.c for the SMT systems. SMT is becoming more popular and is
\tturning up in more and more architectures. I don't think it will be too
\tlong until this feature is supported by most arches...
Now that last sentence seems to indicate that SMT is not far off for desktop processors. It is unknown if the individual actually knows what the future is about to deliver or if he is just geussing about future directions.
It does give me a little hope that the future with SMT is not that far away.
Now the question that comes to mind is this a future with Power5 derived hardware or is it a future with SMT bolted onto a 970. One also has to consider is Power5 just Power4 with SMT bolted on. Yeah I know there is more to it than that but I hope everyone gets the general idea. Personally I think the Power5 derived core would be the path of least resistance.
Thanks
Dave
Originally posted by wizard69
Hi Guys;
Came across something interesting while combing through the change log for the latest Linux kernel. I also posted this snip over on Ars.
Now that last sentence seems to indicate that SMT is not far off for desktop processors. It is unknown if the individual actually knows what the future is about to deliver or if he is just geussing about future directions.
It does give me a little hope that the future with SMT is not that far away.
Now the question that comes to mind is this a future with Power5 derived hardware or is it a future with SMT bolted onto a 970. One also has to consider is Power5 just Power4 with SMT bolted on. Yeah I know there is more to it than that but I hope everyone gets the general idea. Personally I think the Power5 derived core would be the path of least resistance.
Thanks
Dave
My take on this is that he is talking about the 970 and the like. It has been my experience that when people are talking about the POWER series that is how they refer to it POWER. When people are referring to the 970 and the like they say PPC the 64 part just nails it as being 970 like, as opposed to other versions of the PPC that are not 64. Yes it does look like SMT is coming soon like maybe in the March revision time frame. We all knew that clock rate increases at least at the 90 level is expensive, in many ways, to do. So the promise to Apple is performance increases, some equate that only with clock rate others know that there are many different technologies that can come to the PPC 9XX processors and give them significant performance increases and never need to increase the clock rate, not saying that IBM cannot increase the clock rate, but I would rather have these technologies rather than have another 500MHz clock raate increase. I tend to think that these other technologies like SMT, more cores, on die memory controller, rapid IO, improved Altivec, and the like add up to more than 500MHZ performance wise.
Originally posted by Tomb of the Unknown
You mean, "Neither does the POWER4!"
See any Macs with POWER4's in them? No?
Gee, wonder why?
If you run OSX in one of IBM's POWER4 machines, isn't that a POWER4 Mac? Not that I am doing that, I am just asking.
Originally posted by Tidris
If you run OSX in one of IBM's POWER4 machines, isn't that a POWER4 Mac? Not that I am doing that, I am just asking.
Short answer: No.
Long answer: Try it some time.
Originally posted by Tomb of the Unknown
Short answer: No.
Long answer: Try it some time.
And why not? If you hide the POWER4 box under a desk, who would know the difference? My point is that what most people call a "Mac" is not the hardware but the user experience one gets from using the OSX software. If you run LINUX on an Apple G5 machine, is that a Mac? I say absolutely not because the user experience is completely different. So, by my way of thinking, a POWER4/POWER5 Mac is very feasible because all it takes is porting OSX to any of the fine IBM POWER5 boxes. All Apple has to do is refrain from suing whoever is doing the porting .
Originally posted by wizard69
Obviously you can't talk about what you know, but which post here would a wise man ignore?
Nice try.
I'm fairly lucky with what I'm doing now. Totally unrelated to anything discussed here. In fact just the mention of Apple products causes people to ask if they are still in business around here.
Normally I post here freely because I don't know anything about Apple's plans either.
Originally posted by Programmer
Normally I post here freely because I don't know anything about Apple's plans either.
Niether do I so post away I will!
Lots of news coming out lately. Now IBM has indicated that they are moving Hypervisor support or something similar into one of the next PPC chips. If SMT support is there also then I'd have to say it is pretty clear that the next or 2nd to the next PPC is in fact derived from Power5.
Now the question is how soon can Apple and IBM actually deliver working systems? I'm still thinking that something this big will probally wait for WWDC though a big boost at MWSF would be nice.
Dave
Originally posted by Tidris
So, by my way of thinking, a POWER4/POWER5 Mac is very feasible because all it takes is porting OSX to any of the fine IBM POWER5 boxes. All Apple has to do is refrain from suing whoever is doing the porting .
Right, so you go ahead and port it then. I'll just wait over here.