Actually I was starting to wonder about that myself, and started to think of the possibility that if the main PPC core is running at 500MHz, and it has 8 individual cores running off that same frequency it may possibly read, and perform combined as 4GHz.
Huh? Sorry, multiple cores don't "add up" that way. This is a single 2-way SMT in-order dual issue core running at 4 GHz. The pipelines are definitely in the range same range as the Pentium4 (which had ~30 in the last version that reached 3.8 GHz). The lack of complex OoOE support definitely makes this PPE a lot smaller and simpler, and probably allows it to reach these higher clock rates but that does not obviate the need for long pipelines.
As for Merill Lynch... they've repeatedly proven themselves to be wildly speculative. There is a lot of speculation on the 'net right now about Apple and Cell, and in the past ML has mentioned that kind of hypothetical in their market predictions. $102 per share, wow. That's a lot for a company that was down around $10 only a couple of years ago. If achieved that means Apple's market cap will have gone from about 4 billion to 40 billion without a significant change in the size of the company.
Huh? Sorry, multiple cores don't "add up" that way. This is a single 2-way SMT in-order dual issue core running at 4 GHz. The pipelines are definitely in the range same range as the Pentium4 (which had ~30 in the last version that reached 3.8 GHz). The lack of complex OoOE support definitely makes this PPE a lot smaller and simpler, and probably allows it to reach these higher clock rates but that does not obviate the need for long pipelines.
Thanks for straightening that out. You seem to know a lot about this being that no one has ever actually seen, or tested one running outside of IBM, sony, toshiba, or asked these questions of IBM. Do you work there?
The other thing is the cores are actually called SPE's which stands for synergistic processing elements. "Synergistic" itself led to the belief of the possibility because by definition it's meaning is essentially what I described.
Synergistic: \\ "1. Of or relating to synergy: a synergistic effect."
Synergy: \\ 1. The interaction of two or more agents or forces so that their combined effect is greater than the sum of their individual effects. 2. Cooperative interaction among groups, especially among the acquired subsidiaries or merged parts of a corporation, that creates an enhanced combined effect.
But again, I know nothing of these things, and I totally believe you are correct.
I'd say if the stock jumped on "could" being the focus it was premature, but Sony today did announce a new Cell phone that will also have iTunes on board, that actually plays AAC, and they will be showing it at Cebit in March.
and it mentions AAC as one of it's file formats, but no mention of iTunes. If a device can read AAC files does that automatically mean it has iTunes or that it can play AAC files purchased on iTunes?
Sony did not announce iTunes compatibility. They announced their own phones to compete with Motorola's iTunes phone. They will use the Sony Connect store.
and it mentions AAC as one of it's file formats, but no mention of iTunes. If a device can read AAC files does that automatically mean it has iTunes or that it can play AAC files purchased on iTunes?
and it mentions AAC as one of it's file formats, but no mention of iTunes. If a device can read AAC files does that automatically mean it has iTunes or that it can play AAC files purchased on iTunes?
True indeed. I misread the article I saw, being that I only scanned a few pieces.
Quote:
Sony Ericsson Mobile Communications AB will counter Motorola's introduction yesterday of its first iTunes-compatible cell phone when it unveils a mobile phone-cum-digital music player early next month, company President Miles Flint announced at the 3GSM World Congress in Cannes on Monday.
In scanning the article I only noticed two highlights that stood out to me, but also spotted a few other things. Like it is Mac OS X compatible which I find strange being that the walkman MP3 is not Mac friendly. Also support for AAC which is the format chose to convert all my songs to.
Why on earth would anyone think that IBM could make a short pipeline design run at 5.6 GHz when their previous short pipeline designs can barely crack 1 GHz and Motorola's only recently reached a paltry 1.67 GHz?
To play Devil's advocate: Why on Earth would anyone think that Freescale would hitch a 4GHz CPU to a 167MHz SDR bus? The relative immobility of MaxBus has stretched the CPU:bus clock ratio about as far as it can reasonably go, and so Freescale has used almost all their improvements in design and process to reduce cost, power consumption, and "hot spots." That's where their progress has been made for the last couple of years.
Until MaxBus is dead, there's no point even contemplating a design like Cell's that requires massive bandwidth.
And, of course, after MaxBus is dead, the G4 core will not magically become optimized for high Hz. But it should be able to scale up more quickly than it has done.
Quote:
This thing is a long pipeline design, end of story. The whole chip is designed for throughput and pipelining while trying to hide long latencies at every turn, what makes you think that the Power core would be any different?
I agree based on my own intuition, but I'm reading other things from people who know more about these things than I do (at Ars, mostly).
While I have your attention, for my own edification, what is "FO4," and why is IBM so happy to have reduced it?
Quote:
I used to like David Every's writings, but for the last 6 or so years he really hasn't had much to contribute and tends to have too many errors in his articles (this one in particular has quite a few). Charging for it seems ridiculous.
Agreed. RIP MacKiDo. He wasn't always right then, either, but he was right more often, and certainly more interesting, than he's been for a while now.
As for Merill Lynch... they've repeatedly proven themselves to be wildly speculative. There is a lot of speculation on the 'net right now about Apple and Cell, and in the past ML has mentioned that kind of hypothetical in their market predictions. $102 per share, wow. That's a lot for a company that was down around $10 only a couple of years ago. If achieved that means Apple's market cap will have gone from about 4 billion to 40 billion without a significant change in the size of the company.
I have a different point of view on this for a few reasons. While it is true that in the past it was rumored that Apple and IBM would link up, this time things are different. Apple is on a role and riding high, Sony appears lost without direction. The last time it was speculated that they would link up the roles were reversed. It is not hard to imagine that Apple can see the PC wars as over for a long time, but Apple has proven that they have vision and the ability to capitalize on that vision. Apple could make very good if not great appliances especially high tech that could fill the home from streaming MP3s to movies and high def. Apple has many jewels. We being Mac heads tend to only see the computer, but the real strength of Apple of late is the marrying of high tech trends and making it into an appliance. Airport, Airport extreme, rendezvous, integrating, weaving the software glue that holds together the hardware for doing all sorts of things that may or may not have the computer at the center. Just as Honda views itself as a world class engine manufacturer that also makes cars, and Fed-Ex sees itself as a world class logistics provider that also delivers packages, Apple, I believe, sees itself as a world class software and hardware standards integrator that also sells computers.
In the past Apple has called upon Sony to manufacture their laptops. I can see Apple having Sony OEM any number of home centered digital devices to compliment Apple's product lines.
Sony will want to use their investment in Cell to produce products containing them, regardless of what logo appears on the front of those products. As Brendon just posted, Apple has a lot to offer Sony and others.
If Apple does decide to make the jump to IPTV I could easily see Sony building the box that does it for them.
Thanks for straightening that out. You seem to know a lot about this being that no one has ever actually seen, or tested one running outside of IBM, sony, toshiba, or asked these questions of IBM. Do you work there?
Everything I've said in the forums is evident from what has been announced publicly. Having a reasonably solid understanding of hardware and software technology helps greatly in interpreting the press releases, presentations, and articles on Arts, RWT, etc.
To play Devil's advocate: Why on Earth would anyone think that Freescale would hitch a 4GHz CPU to a 167MHz SDR bus? The relative immobility of MaxBus has stretched the CPU:bus clock ratio about as far as it can reasonably go, and so Freescale has used almost all their improvements in design and process to reduce cost, power consumption, and "hot spots." That's where their progress has been made for the last couple of years.
Until MaxBus is dead, there's no point even contemplating a design like Cell's that requires massive bandwidth.
And, of course, after MaxBus is dead, the G4 core will not magically become optimized for high Hz. But it should be able to scale up more quickly than it has done.
Sorry, but I don't see the analogy. IBM could have chosen to mate their 4+ GHz design to an MPX bus, or even a 1 Hz binary blinking light -- that is easily technically achieveable. Building a short pipeline 4 GHz design is not technically achieveable.
It is also unlikely that Freescale has the technical wherewithal to achieve what STI has. They simply don't have the brain trust and process capabilities.
Quote:
I agree based on my own intuition, but I'm reading other things from people who know more about these things than I do (at Ars, mostly).
Lots of people write lots of things that are just completely bogus. Stick with your intuition on this one.
Quote:
While I have your attention, for my own edification, what is "FO4," and why is IBM so happy to have reduced it?
I believe that FO stands for "fan out"... a quick Google turns up this:
Building a short pipeline 4 GHz design is not technically achieveable.
Doing that with all the control logic baggage would be unachievable. Eliminating that overhead not only removes the necessity to power it, but also has a stupendous effect on reducing signal synchronization complexity. When you make the overall system simple enough it's easier to make it go fast together, where an almost simple enough would only get you a disaster trying to go that fast.
Effective complexity to an instruction is much more involved than the stages in the execution units alone. And removing unneeded complexity externally makes it much easier to optimize locally within those leftover pieces. Pipeline stages were more an effect necessary for signal propagation and synchronization than necessary for their own existence. They add complexity simply by being there because getting single threads instructions through the most complex machines devised by mans will required the sacrifice of yet more complexity. See a spiral going here? I know you do. PPE & SPEs essentially are independent units which decouple their complexity from each other. The number of transistors which directly depend on the interrelated operation of other transistors is cut by over an order of magnitude from conventional RISC/CISC processors. Now look at it backwards and don't be quite so skeptical of the effects you see from reducing overall complexity by that order of magnitude. Everything is relative.
Doing that with all the control logic baggage would be unachievable. Eliminating that overhead not only removes the necessity to power it, but also has a stupendous effect on reducing signal synchronization complexity. When you make the overall system simple enough it's easier to make it go fast together, where an almost simple enough would only get you a disaster trying to go that fast.
Effective complexity to an instruction is much more involved than the stages in the execution units alone. And removing unneeded complexity externally makes it much easier to optimize locally within those leftover pieces. Pipeline stages were more an effect necessary for signal propagation and synchronization than necessary for their own existence. They add complexity simply by being there because getting single threads instructions through the most complex machines devised by mans will required the sacrifice of yet more complexity. See a spiral going here? I know you do. PPE & SPEs essentially are independent units which decouple their complexity from each other. The number of transistors which directly depend on the interrelated operation of other transistors is cut by over an order of magnitude from conventional RISC/CISC processors. Now look at it backwards and don't be quite so skeptical of the effects you see from reducing overall complexity by that order of magnitude. Everything is relative.
Excellent post! With the increasing number of cores OoE makes less sense. (See my older postings.) I think this is the start of a paradigm shift, instead of making the cores more complex and intelligent, make more stupid simple cores. There seems to be confusion about the length of the pipeline and frequence. The problem is not that shorter pipelines can't be clocked high, the problem is the saturation of the units within the pipeline. (This is why OoE was introduced.)
Excellent post! With the increasing number of cores OoE makes less sense. (See my older postings.) I think this is the start of a paradigm shift, instead of making the cores more complex and intelligent, make more stupid simple cores. There seems to be confusion about the length of the pipeline and frequence. The problem is not that shorter pipelines can't be clocked high, the problem is the saturation of the units within the pipeline. (This is why OoE was introduced.)
It was an excellent post, and it clearly states why OoOE is losing its value. Longer pipelines, however, reduce the local per-stage complexity which is often the gating factor on clock rate. SMT is also complex, but is provided to improve resource utilization in long pipelines which are stalling.
This initial Cell chip is very clearly the first wave of the paradigm shift you describe. That's the whole point of it. They are relying on carefully optimized software to achieve maximum performance, and just assuming that the rest of the software is "fast enough" on current processors. By and large they are right, but for developers who have been riding the wave of fast OoOE chips there is going to be some pain as they finally run face first into the realities that they've been ignoring.
It's just not quite that easy to go with my intuition. My intuition rejected a $500 headless Mac out of hand, and look what that got me.
My point with MaxBus was that there was no reason for Freescale to release an architecture that even tried to be like Cell. This might disguise an inability on their part to even pull it off, but even that won't be relevant until they move the memory controller on-die. Even then, the G4 and successors won't be dealing with anything like Cell's bandwidth.
But, is it technically infeasible to have a short pipeline clocked high? Conventional processor design says yes, but Cell is not a conventional processor design. IBM have apparently taken some fairly radical steps to speed up the logic itself, and of course they also blew away all the control logic. A first proof of what would become Cell technology did get an all-integer G3 core up to 1GHz back in 2000 or so. Freescale seems casually optimistic about getting the 7-stage 7448 over 2GHz, and that design dates from the wide-issue, superscalar era (even if it's a modest example of the style). And, of course, "short pipelines" means "short for something that clocks so high," not necessarily 4 or 5 or 7 stages.
It's just not quite that easy to go with my intuition. My intuition rejected a $500 headless Mac out of hand, and look what that got me.
My point with MaxBus was that there was no reason for Freescale to release an architecture that even tried to be like Cell. This might disguise an inability on their part to even pull it off, but even that won't be relevant until they move the memory controller on-die. Even then, the G4 and successors won't be dealing with anything like Cell's bandwidth.
But, is it technically infeasible to have a short pipeline clocked high? Conventional processor design says yes, but Cell is not a conventional processor design. IBM have apparently taken some fairly radical steps to speed up the logic itself, and of course they also blew away all the control logic. A first proof of what would become Cell technology did get an all-integer G3 core up to 1GHz back in 2000 or so. Freescale seems casually optimistic about getting the 7-stage 7448 over 2GHz, and that design dates from the wide-issue, superscalar era (even if it's a modest example of the style). And, of course, "short pipelines" means "short for something that clocks so high," not necessarily 4 or 5 or 7 stages.
Curse this paucity of public documentation.
Amorph, you brought up the on-die memory controller so I have to ask is there any word on IBM using it in future upcoming versions of the PPC?
Amorph, you brought up the on-die memory controller so I have to ask is there any word on IBM using it in future upcoming versions of the PPC?
Well, Cell's using one, and it contains a PPC. Presumably anything else that uses the PPE (IBM's name for the PPC core within Cell) will also use an onboard memory controller, even if it's not the same one on the current Cell processor.
Beyond that, I don't know. I actually don't expect future versions of the PPC9xx line to use one, given all the work that went into Elastic Bus. But with other lines, who knows?
Well, Cell's using one, and it contains a PPC. Presumably anything else that uses the PPE (IBM's name for the PPC core within Cell) will also use an onboard memory controller, even if it's not the same one on the current Cell processor.
Bad presumption. According to the diagrams, the Cell's memory controller is a node on the on-chip bus, not part of the PPE. Eliminate the on-chip bus and the two have nothing to do with eachother (that's the beauty of the modular Cell design).
Re: G4 / MPX: I see your point now, but I don't believe it at all. Motorola/Freescale have been inching the G4 upward for years, always behind their own roadmap. Same applies to the IBM G3 and its roadmap. If you won't believe your intuition on this one, then just take my word for it.
Comments
Originally posted by onlooker
Actually I was starting to wonder about that myself, and started to think of the possibility that if the main PPC core is running at 500MHz, and it has 8 individual cores running off that same frequency it may possibly read, and perform combined as 4GHz.
Huh? Sorry, multiple cores don't "add up" that way. This is a single 2-way SMT in-order dual issue core running at 4 GHz. The pipelines are definitely in the range same range as the Pentium4 (which had ~30 in the last version that reached 3.8 GHz). The lack of complex OoOE support definitely makes this PPE a lot smaller and simpler, and probably allows it to reach these higher clock rates but that does not obviate the need for long pipelines.
As for Merill Lynch... they've repeatedly proven themselves to be wildly speculative. There is a lot of speculation on the 'net right now about Apple and Cell, and in the past ML has mentioned that kind of hypothetical in their market predictions. $102 per share, wow. That's a lot for a company that was down around $10 only a couple of years ago. If achieved that means Apple's market cap will have gone from about 4 billion to 40 billion without a significant change in the size of the company.
Originally posted by Programmer
Huh? Sorry, multiple cores don't "add up" that way. This is a single 2-way SMT in-order dual issue core running at 4 GHz. The pipelines are definitely in the range same range as the Pentium4 (which had ~30 in the last version that reached 3.8 GHz). The lack of complex OoOE support definitely makes this PPE a lot smaller and simpler, and probably allows it to reach these higher clock rates but that does not obviate the need for long pipelines.
Thanks for straightening that out. You seem to know a lot about this being that no one has ever actually seen, or tested one running outside of IBM, sony, toshiba, or asked these questions of IBM. Do you work there?
Synergistic: \\ "1. Of or relating to synergy: a synergistic effect."
Synergy: \\ 1. The interaction of two or more agents or forces so that their combined effect is greater than the sum of their individual effects. 2. Cooperative interaction among groups, especially among the acquired subsidiaries or merged parts of a corporation, that creates an enhanced combined effect.
But again, I know nothing of these things, and I totally believe you are correct.
Originally posted by onlooker
I'd say if the stock jumped on "could" being the focus it was premature, but Sony today did announce a new Cell phone that will also have iTunes on board, that actually plays AAC, and they will be showing it at Cebit in March.
Got a link on that? I found this: http://www.sonyericsson.com/spg.jsp?...c3_1&prid=2827
and it mentions AAC as one of it's file formats, but no mention of iTunes. If a device can read AAC files does that automatically mean it has iTunes or that it can play AAC files purchased on iTunes?
Originally posted by WelshDog
Got a link on that? I found this: http://www.sonyericsson.com/spg.jsp?...c3_1&prid=2827
and it mentions AAC as one of it's file formats, but no mention of iTunes. If a device can read AAC files does that automatically mean it has iTunes or that it can play AAC files purchased on iTunes?
Originally posted by WelshDog
Got a link on that? I found this: http://www.sonyericsson.com/spg.jsp?...c3_1&prid=2827
and it mentions AAC as one of it's file formats, but no mention of iTunes. If a device can read AAC files does that automatically mean it has iTunes or that it can play AAC files purchased on iTunes?
True indeed. I misread the article I saw, being that I only scanned a few pieces.
Sony Ericsson Mobile Communications AB will counter Motorola's introduction yesterday of its first iTunes-compatible cell phone when it unveils a mobile phone-cum-digital music player early next month, company President Miles Flint announced at the 3GSM World Congress in Cannes on Monday.
In scanning the article I only noticed two highlights that stood out to me, but also spotted a few other things. Like it is Mac OS X compatible which I find strange being that the walkman MP3 is not Mac friendly. Also support for AAC which is the format chose to convert all my songs to.
I'm certain we'll know more about it after Cebit.
Originally posted by Programmer
Why on earth would anyone think that IBM could make a short pipeline design run at 5.6 GHz when their previous short pipeline designs can barely crack 1 GHz and Motorola's only recently reached a paltry 1.67 GHz?
To play Devil's advocate: Why on Earth would anyone think that Freescale would hitch a 4GHz CPU to a 167MHz SDR bus? The relative immobility of MaxBus has stretched the CPU:bus clock ratio about as far as it can reasonably go, and so Freescale has used almost all their improvements in design and process to reduce cost, power consumption, and "hot spots." That's where their progress has been made for the last couple of years.
Until MaxBus is dead, there's no point even contemplating a design like Cell's that requires massive bandwidth.
And, of course, after MaxBus is dead, the G4 core will not magically become optimized for high Hz. But it should be able to scale up more quickly than it has done.
This thing is a long pipeline design, end of story. The whole chip is designed for throughput and pipelining while trying to hide long latencies at every turn, what makes you think that the Power core would be any different?
I agree based on my own intuition, but I'm reading other things from people who know more about these things than I do (at Ars, mostly).
While I have your attention, for my own edification, what is "FO4," and why is IBM so happy to have reduced it?
I used to like David Every's writings, but for the last 6 or so years he really hasn't had much to contribute and tends to have too many errors in his articles (this one in particular has quite a few). Charging for it seems ridiculous.
Agreed. RIP MacKiDo. He wasn't always right then, either, but he was right more often, and certainly more interesting, than he's been for a while now.
Originally posted by Programmer
As for Merill Lynch... they've repeatedly proven themselves to be wildly speculative. There is a lot of speculation on the 'net right now about Apple and Cell, and in the past ML has mentioned that kind of hypothetical in their market predictions. $102 per share, wow. That's a lot for a company that was down around $10 only a couple of years ago. If achieved that means Apple's market cap will have gone from about 4 billion to 40 billion without a significant change in the size of the company.
I have a different point of view on this for a few reasons. While it is true that in the past it was rumored that Apple and IBM would link up, this time things are different. Apple is on a role and riding high, Sony appears lost without direction. The last time it was speculated that they would link up the roles were reversed. It is not hard to imagine that Apple can see the PC wars as over for a long time, but Apple has proven that they have vision and the ability to capitalize on that vision. Apple could make very good if not great appliances especially high tech that could fill the home from streaming MP3s to movies and high def. Apple has many jewels. We being Mac heads tend to only see the computer, but the real strength of Apple of late is the marrying of high tech trends and making it into an appliance. Airport, Airport extreme, rendezvous, integrating, weaving the software glue that holds together the hardware for doing all sorts of things that may or may not have the computer at the center. Just as Honda views itself as a world class engine manufacturer that also makes cars, and Fed-Ex sees itself as a world class logistics provider that also delivers packages, Apple, I believe, sees itself as a world class software and hardware standards integrator that also sells computers.
My 2¢
Sony will want to use their investment in Cell to produce products containing them, regardless of what logo appears on the front of those products. As Brendon just posted, Apple has a lot to offer Sony and others.
If Apple does decide to make the jump to IPTV I could easily see Sony building the box that does it for them.
Originally posted by onlooker
Thanks for straightening that out. You seem to know a lot about this being that no one has ever actually seen, or tested one running outside of IBM, sony, toshiba, or asked these questions of IBM. Do you work there?
Everything I've said in the forums is evident from what has been announced publicly. Having a reasonably solid understanding of hardware and software technology helps greatly in interpreting the press releases, presentations, and articles on Arts, RWT, etc.
Originally posted by Amorph
To play Devil's advocate: Why on Earth would anyone think that Freescale would hitch a 4GHz CPU to a 167MHz SDR bus? The relative immobility of MaxBus has stretched the CPU:bus clock ratio about as far as it can reasonably go, and so Freescale has used almost all their improvements in design and process to reduce cost, power consumption, and "hot spots." That's where their progress has been made for the last couple of years.
Until MaxBus is dead, there's no point even contemplating a design like Cell's that requires massive bandwidth.
And, of course, after MaxBus is dead, the G4 core will not magically become optimized for high Hz. But it should be able to scale up more quickly than it has done.
Sorry, but I don't see the analogy. IBM could have chosen to mate their 4+ GHz design to an MPX bus, or even a 1 Hz binary blinking light -- that is easily technically achieveable. Building a short pipeline 4 GHz design is not technically achieveable.
It is also unlikely that Freescale has the technical wherewithal to achieve what STI has. They simply don't have the brain trust and process capabilities.
I agree based on my own intuition, but I'm reading other things from people who know more about these things than I do (at Ars, mostly).
Lots of people write lots of things that are just completely bogus. Stick with your intuition on this one.
While I have your attention, for my own edification, what is "FO4," and why is IBM so happy to have reduced it?
I believe that FO stands for "fan out"... a quick Google turns up this:
http://www.realworldtech.com/page.cf...WT081502231107
Originally posted by Programmer
Building a short pipeline 4 GHz design is not technically achieveable.
Doing that with all the control logic baggage would be unachievable. Eliminating that overhead not only removes the necessity to power it, but also has a stupendous effect on reducing signal synchronization complexity. When you make the overall system simple enough it's easier to make it go fast together, where an almost simple enough would only get you a disaster trying to go that fast.
Effective complexity to an instruction is much more involved than the stages in the execution units alone. And removing unneeded complexity externally makes it much easier to optimize locally within those leftover pieces. Pipeline stages were more an effect necessary for signal propagation and synchronization than necessary for their own existence. They add complexity simply by being there because getting single threads instructions through the most complex machines devised by mans will required the sacrifice of yet more complexity. See a spiral going here? I know you do. PPE & SPEs essentially are independent units which decouple their complexity from each other. The number of transistors which directly depend on the interrelated operation of other transistors is cut by over an order of magnitude from conventional RISC/CISC processors. Now look at it backwards and don't be quite so skeptical of the effects you see from reducing overall complexity by that order of magnitude. Everything is relative.
Originally posted by Hiro
Doing that with all the control logic baggage would be unachievable. Eliminating that overhead not only removes the necessity to power it, but also has a stupendous effect on reducing signal synchronization complexity. When you make the overall system simple enough it's easier to make it go fast together, where an almost simple enough would only get you a disaster trying to go that fast.
Effective complexity to an instruction is much more involved than the stages in the execution units alone. And removing unneeded complexity externally makes it much easier to optimize locally within those leftover pieces. Pipeline stages were more an effect necessary for signal propagation and synchronization than necessary for their own existence. They add complexity simply by being there because getting single threads instructions through the most complex machines devised by mans will required the sacrifice of yet more complexity. See a spiral going here? I know you do. PPE & SPEs essentially are independent units which decouple their complexity from each other. The number of transistors which directly depend on the interrelated operation of other transistors is cut by over an order of magnitude from conventional RISC/CISC processors. Now look at it backwards and don't be quite so skeptical of the effects you see from reducing overall complexity by that order of magnitude. Everything is relative.
Excellent post! With the increasing number of cores OoE makes less sense. (See my older postings.) I think this is the start of a paradigm shift, instead of making the cores more complex and intelligent, make more stupid simple cores. There seems to be confusion about the length of the pipeline and frequence. The problem is not that shorter pipelines can't be clocked high, the problem is the saturation of the units within the pipeline. (This is why OoE was introduced.)
End of Line
Originally posted by User Tron
Excellent post! With the increasing number of cores OoE makes less sense. (See my older postings.) I think this is the start of a paradigm shift, instead of making the cores more complex and intelligent, make more stupid simple cores. There seems to be confusion about the length of the pipeline and frequence. The problem is not that shorter pipelines can't be clocked high, the problem is the saturation of the units within the pipeline. (This is why OoE was introduced.)
It was an excellent post, and it clearly states why OoOE is losing its value. Longer pipelines, however, reduce the local per-stage complexity which is often the gating factor on clock rate. SMT is also complex, but is provided to improve resource utilization in long pipelines which are stalling.
This initial Cell chip is very clearly the first wave of the paradigm shift you describe. That's the whole point of it. They are relying on carefully optimized software to achieve maximum performance, and just assuming that the rest of the software is "fast enough" on current processors. By and large they are right, but for developers who have been riding the wave of fast OoOE chips there is going to be some pain as they finally run face first into the realities that they've been ignoring.
My point with MaxBus was that there was no reason for Freescale to release an architecture that even tried to be like Cell. This might disguise an inability on their part to even pull it off, but even that won't be relevant until they move the memory controller on-die. Even then, the G4 and successors won't be dealing with anything like Cell's bandwidth.
But, is it technically infeasible to have a short pipeline clocked high? Conventional processor design says yes, but Cell is not a conventional processor design. IBM have apparently taken some fairly radical steps to speed up the logic itself, and of course they also blew away all the control logic. A first proof of what would become Cell technology did get an all-integer G3 core up to 1GHz back in 2000 or so. Freescale seems casually optimistic about getting the 7-stage 7448 over 2GHz, and that design dates from the wide-issue, superscalar era (even if it's a modest example of the style). And, of course, "short pipelines" means "short for something that clocks so high," not necessarily 4 or 5 or 7 stages.
Curse this paucity of public documentation.
Originally posted by Amorph
It's just not quite that easy to go with my intuition. My intuition rejected a $500 headless Mac out of hand, and look what that got me.
My point with MaxBus was that there was no reason for Freescale to release an architecture that even tried to be like Cell. This might disguise an inability on their part to even pull it off, but even that won't be relevant until they move the memory controller on-die. Even then, the G4 and successors won't be dealing with anything like Cell's bandwidth.
But, is it technically infeasible to have a short pipeline clocked high? Conventional processor design says yes, but Cell is not a conventional processor design. IBM have apparently taken some fairly radical steps to speed up the logic itself, and of course they also blew away all the control logic. A first proof of what would become Cell technology did get an all-integer G3 core up to 1GHz back in 2000 or so. Freescale seems casually optimistic about getting the 7-stage 7448 over 2GHz, and that design dates from the wide-issue, superscalar era (even if it's a modest example of the style). And, of course, "short pipelines" means "short for something that clocks so high," not necessarily 4 or 5 or 7 stages.
Curse this paucity of public documentation.
Amorph, you brought up the on-die memory controller so I have to ask is there any word on IBM using it in future upcoming versions of the PPC?
Originally posted by onlooker
Amorph, you brought up the on-die memory controller so I have to ask is there any word on IBM using it in future upcoming versions of the PPC?
Well, Cell's using one, and it contains a PPC. Presumably anything else that uses the PPE (IBM's name for the PPC core within Cell) will also use an onboard memory controller, even if it's not the same one on the current Cell processor.
Beyond that, I don't know. I actually don't expect future versions of the PPC9xx line to use one, given all the work that went into Elastic Bus. But with other lines, who knows?
Originally posted by Amorph
Well, Cell's using one, and it contains a PPC. Presumably anything else that uses the PPE (IBM's name for the PPC core within Cell) will also use an onboard memory controller, even if it's not the same one on the current Cell processor.
Bad presumption. According to the diagrams, the Cell's memory controller is a node on the on-chip bus, not part of the PPE. Eliminate the on-chip bus and the two have nothing to do with eachother (that's the beauty of the modular Cell design).
Re: G4 / MPX: I see your point now, but I don't believe it at all. Motorola/Freescale have been inching the G4 upward for years, always behind their own roadmap. Same applies to the IBM G3 and its roadmap. If you won't believe your intuition on this one, then just take my word for it.