Bus Definitions and Tech Talk:

dstranathandstranathan
Posted:
in Future Apple Hardware edited January 2014
Can somebody please give me a lenghty, detailed definition of both frontside and backside buses? Specifically in Mac G4 and G5 computers.



I would like to better understand which bus talks to PCI/AGP, controllers, etc, and what bus talks to Memory, Altivec, Cache, ROMs/Firmware, etc. Info on speeds and bandwidth would be nice.



All this talk about the "guts" of current G4s and hypothetical G5's has me a bit confused.



The geekier the better, but an overview would be nice also. Maybe even compare Macs to PC Mobo design involving both bus design and implimention of chipsets (compare and contrast the 2 platforms)



Is MMX on the PC still around? Apple sure boasts about Altivec, but Intel dropped the "With MMX inside" propaganda a long time ago.



Also- is it true that IBM plans on putting stickers on Mac that says "Built with IBM PPC" or whatever? Heck, Macs dont even have the "PPC" logo on them anymore. (Apple even removed the APPLE logo on the front of the Quicksilvers!)



Why does Apple still use ATA/66 and 5400 RPM drives?



Thanks!

Comments

  • Reply 1 of 3
    whisperwhisper Posts: 735member
    Poke around at <a href="http://www.arstechnica.com"; target="_blank">Ars Technica</a>.



    edit: spelling



    [ 12-21-2001: Message edited by: Whisper ]</p>
  • Reply 2 of 3
    msleemslee Posts: 143member
    heh,



    ill give you the standard ars answer.



    Google is you friend

    <a href="http://www.google.com/search?q=definition+of+a+front+side+bus"; target="_blank">start here</a>
  • Reply 3 of 3
    randycat99randycat99 Posts: 1,919member
    Isn't MMX something entirely different from Altivec? Something more comparable on the PC side would be SSE and SSE2. SSE, SSE2, and Altivec involve vector computations.



    I've been doing a bit of research on buses, myself, lately. This is actually where a lot of interesting stuff is going on right now. I've been reading about system buses in different CPU's, chipset buses, and memory buses with respect to PIII/celeron, G3/G4, P4, Rambus and DDR systems, AGP, Xbox (nForce motherboard), PS2, and GC.



    I've spent quite a bit of time perusing the details of this stuff at ArsTechnica blackpapers, AnandTech motherboard reviews and hardware review articles, and Tomshardware hardware review articles.



    The basic technique to get an indicator of peak bandwidth of a bus involves finding out the bit-width (16-bit, 64-bit, 128-bit, 256-bit, ...) and the operating frequency (66 Mhz, 100 Mhz, 133 Mhz, 150 Mhz, ...). Then you take the bit-width, divide by 8, and multiply by the operating frequency. The result will be xyz MB/s. If you divide that number by 1000, then the result will be in GB/s. If the bus is using some kind of DDR (such as in a DDR SRAM memory system) or QDR (such as in the FSB of the P4) strategy, then you multiply by 2 or 4, respectively, to get the proper peak bus bandwidth.



    Obviously there's much more beyond that, but I just wanted to give you a little start.



    [ 12-22-2001: Message edited by: Randycat99 ]</p>
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