MojaveMP = G5 and 970/GPUL = G6?
A snippet from <a href="http://www.macedition.com/nmr/nmr_20030122.php"; target="_blank">http://www.macedition.com/nmr/nmr_20030122.php</a>; and the Naked Mole Rat (aka Mac the Knife)
[quote] As has been reported in part by other Mac-o-philic worthies, the company has now navigated beyond its Sahara generation of PowerPC G3 to a remap dubbed Colorado. Next stop: Gobi, which is expected to reach full production during the first calendar quarter of 2003.
But what lies beyond Gobi? Instead of continuing to rev the PowerPC G3?s hoary 7xx architecture, the Blade?s yurt-carriers aver, Gobi?s planned successor, code-named MojaveMP, will based on the nascent Viper template, which in turn will represent a grand union between the 7xx and IBM?s 4xx series of embedded processors.
Mojave, which will start at 1.6 GHz, will be based on a 0.10-nanometer process and feature dynamic voltage and frequency scaling. As a result, this bantamweight will be able to run at its base speed at 1.2 V and eat up only a Callista Flockhart-size 10 W.
But what of the eagerly awaited PowerPC 970, a k a GPUL? After a year or so of production (at speeds of up to 1.8 GHz), IBM plans to pop out a 970+, which should include a few niceties that will bring it to 2.5 GHz. While much remains obscured beneath the burning sands, there is an undefined ?Next Generation? chip - and it?s not based on the GPUL but the Power5 successor to IBM?s current server silicon. Haha te whenua, haha te tangata! <hr></blockquote>
Why not up both processor lines at a time?
Get the next gen G3 into the iBooks and such (maybe iMacs/eMacs as well) and then have a 970 in the PowerMacs, Xserve, and (possible?) PowerBooks.
While changing the new processors, call 'em G5 and G6. Nice name refresh accross the line.
Thoughts
[quote] As has been reported in part by other Mac-o-philic worthies, the company has now navigated beyond its Sahara generation of PowerPC G3 to a remap dubbed Colorado. Next stop: Gobi, which is expected to reach full production during the first calendar quarter of 2003.
But what lies beyond Gobi? Instead of continuing to rev the PowerPC G3?s hoary 7xx architecture, the Blade?s yurt-carriers aver, Gobi?s planned successor, code-named MojaveMP, will based on the nascent Viper template, which in turn will represent a grand union between the 7xx and IBM?s 4xx series of embedded processors.
Mojave, which will start at 1.6 GHz, will be based on a 0.10-nanometer process and feature dynamic voltage and frequency scaling. As a result, this bantamweight will be able to run at its base speed at 1.2 V and eat up only a Callista Flockhart-size 10 W.
But what of the eagerly awaited PowerPC 970, a k a GPUL? After a year or so of production (at speeds of up to 1.8 GHz), IBM plans to pop out a 970+, which should include a few niceties that will bring it to 2.5 GHz. While much remains obscured beneath the burning sands, there is an undefined ?Next Generation? chip - and it?s not based on the GPUL but the Power5 successor to IBM?s current server silicon. Haha te whenua, haha te tangata! <hr></blockquote>
Why not up both processor lines at a time?
Get the next gen G3 into the iBooks and such (maybe iMacs/eMacs as well) and then have a 970 in the PowerMacs, Xserve, and (possible?) PowerBooks.
While changing the new processors, call 'em G5 and G6. Nice name refresh accross the line.
Thoughts
Comments
But in Apple's 'fight for your life' position...it'd be no less criminal than AMD's 'XP' rating.
As for 970 as a G6? Well, marketing could go that way if G5 gets tagged onto a G3++.
It's all down to Apple and IBM.
I guess you could argue that technically, the above CPUs are just third and fourth generations on turbo boost.
Help?
Lemon Bon Bon
Lemon Bon Bon
Hmmmm. Yummy.
Stick that in yer 17 inch Laptop/iMac2.
Heaven.
Lemon Bon Bon
If the G5 will be the 970, it would look a bit daft to name the new G3 a G6 and even worse to leave it called a G3 (5years later...).
The processor line needs to be refereshed and for salesmen and industry say "New Macs with a G5 and G6 processor..."
What isnt clear is when this MojaveMP should be available. Are we talking about approx same timeframe? cant really have the 970 come out before and call it G6 and then wait a few months and have the Mojave called a G5.
Anyway, yet something else to think of.
PS Yes I know the article is a bit old, but this subject hasnt been touched afaik
<strong>When he says "union of the 7xx and 4xx" I hope that means putting a full 32-bit PowerPC core w/ FPU & VMX in the "system on a chip" 4xx template. That would essentially give us the much-vaunted 7457-RM, but in a lower power package. At the clock rates speculated that would be quite a chip for a mobile computer. Full DDR333 bandwidth too. Wow.</strong><hr></blockquote>
I'm under the impression the 4XX series are still on either a 133MHz. or 167MHz. bus <img src="confused.gif" border="0">
<strong>
I'm under the impression the 4XX series are still on either a 133MHz. or 167MHz. bus
The 44x has an on-chip memory controller that supports DDR333. No FSB.
<strong>
Hmmmm. Yummy.
Stick that in yer 17 inch Laptop/iMac2.</strong><hr></blockquote>
Make that 2 please. <img src="graemlins/cancer.gif" border="0" alt="[cancer]" />
<strong>Maybe Apple will drop the whole Gn notation completely and just call them all PowerPCs. It's not like you can choose which CPU you get in your Mac.</strong><hr></blockquote>
And how could that possibly be an effective marketing scheme? Why don't we just dispense with all of the model names Toyota currently has. Whether they're V4 engines or V8s, you can't change the engine in your car, so they should all simply be called Toyotas.
One thing is more or less sure: Apple needs PPC970. It's likely that they will put them in all of their products.
<strong>
The 44x has an on-chip memory controller that supports DDR333. No FSB.</strong><hr></blockquote>
Thanks, I guess I was confused by IBM's Processor Local Bus(PLB). They show the DDRsdram controller accessing the core through the PLB at up to 166MHz. And they show the PLB communicating through the L2/sram controller before the core.
me remains continually in a state of confusion.
<a href="http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/BC66F5BE37FA67C887256C300056A7D5/$file/PPC440GX.pdf"; target="_blank">Source of My Confusion</a>
Forgot to add that throughout the literature the letters PDA are mentioned by IBM frequently. Just to raise the Apple PDA spectre again <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
[ 02-20-2003: Message edited by: rickag ]</p>
<strong>
Thanks, I guess I was confused by IBM's Processor Local Bus(PLB). They show the DDRsdram controller accessing the core through the PLB at up to 166MHz. And they show the PLB communicating through the L2/sram controller before the core.
me remains continually in a state of confusion.
<a href="http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/BC66F5BE37FA67C887256C300056A7D5/$file/PPC440GX.pdf"; target="_blank">Source of My Confusion</a>
Forgot to add that throughout the literature the letters PDA are mentioned by IBM frequently. Just to raise the Apple PDA spectre again <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
</strong><hr></blockquote>
These chips are also only running at 600-700 MHz. If the SoC stuff were mated to a 1.6 GHz 7xx core the clock rate of the internal bus (and possibly the width as well) would be substantially increased. The nice thing about internal buses is that they are more easily ramped up to much higher speeds.
<strong>
These chips are also only running at 600-700 MHz. If the SoC stuff were mated to a 1.6 GHz 7xx core the clock rate of the internal bus (and possibly the width as well) would be substantially increased. The nice thing about internal buses is that they are more easily ramped up to much higher speeds.</strong><hr></blockquote>
But then it might work for a PDA <img src="graemlins/surprised.gif" border="0" alt="[surprised]" />
just kidding, and again thanks for the information