970MP doesn't support chip-to-Chip communication?
Look at this blurb from the PDF on the Powermac G5 specs. If I'm reading this correctly it states that the 970mp is just like the Pentium D in that it uses the FSB for chip to chip communication. Thus I wouldn't expect to see any efficiencis in dual core performance based on the procs being on the same die.
I'm not sure how it increases performance over the Opteron's system of high speed links between the cores. Intels Conroe should perform better as well since the cache is a continguous shared pool.
Quote:
In Power Mac G5 Quad systems, each processor has its own bidirectional interface
to the system controller, unlike traditional dual-processor systems, which constrain
throughput by placing all processor resources on one bus. Each G5 processor has
a dedicated interface to main memory for total bandwidth of up to 10 GBps per
processor, or a total of 20 GBps for a quad system. This high-performance frontside
bus architecture also enables each core to discover and access data in the other cores?
caches?further increasing performance on quad-core systems.
In Power Mac G5 Quad systems, each processor has its own bidirectional interface
to the system controller, unlike traditional dual-processor systems, which constrain
throughput by placing all processor resources on one bus. Each G5 processor has
a dedicated interface to main memory for total bandwidth of up to 10 GBps per
processor, or a total of 20 GBps for a quad system. This high-performance frontside
bus architecture also enables each core to discover and access data in the other cores?
caches?further increasing performance on quad-core systems.
I'm not sure how it increases performance over the Opteron's system of high speed links between the cores. Intels Conroe should perform better as well since the cache is a continguous shared pool.
Comments
So even if there is a penalty because the two cores share the same bus, the direct interconnection between the two cores is big plus, over the previous generation of dual.
Originally posted by Powerdoc
there is no direct chip communication. The chips communicate via the bus. But the two cores communicates between them directly.
So I take it two i/o bound apps are going to have a cow when run on a single-dual machine like the 2.3. But one app that is multi-processor aware should do really well.
I'll ask the question - is FCP multi-processor aware?
Originally posted by bjewett
So I take it two i/o bound apps are going to have a cow when run on a single-dual machine like the 2.3. But one app that is multi-processor aware should do really well.
I'll ask the question - is FCP multi-processor aware?
Final cut pro is MP aware. (if it was not the case the quad 2,5 would never be faster than a dual 2,7 ...)
Now for the limitating factor of the bus, I doubt it is has huge. My Imac G5 1,8 has only a 600 mhz bus, and it's not that lame compared to a single powermac 1,8. The new mobo is certainly improved compared to the older one.
Originally posted by hmurchison
That's not what Apple's page is stating. They specifically state that each core communicates via the front side bus. We have the IMB equivalent to the Pentium D here.
Actually what it says is "also enables each core to discover and access data in the other cores? caches"
It does not say that is the only communication between the cores, but then again It's not disputing anything your saying either.
Originally posted by hmurchison
That's not what Apple's page is stating. They specifically state that each core communicates via the front side bus. We have the IMB equivalent to the Pentium D here.
I must admit that the Apple page is not very clear. But I am nearly sure that the dual core is not like the pentium D at all. There is interconnection between the two cores. I have read somewhere that the two cores can communicate via the caches.
Originally posted by hmurchison
That's not what Apple's page is stating. They specifically state that each core communicates via the front side bus. We have the IMB equivalent to the Pentium D here.
I think the guys that take care of the content in these pages, screwed somehow the phrasing.
Why IBM develop a new version of dual core G5, when from the leaked IBM document last spring we know that their dual core G5 had already inter-core communication? I find quite possible that the Apple page, when referring to FSB communication between cores, means communication between cores not on the same chip (processor). Is there similar wording for the other (non-quad) 970MP machines? If not, then we have one indication that I may be right.
In Power Mac G5 Quad systems, each processor has its own bidirectional interface to the system controller, unlike traditional dual-processor systems, which constrain throughput by placing all processor resources on one bus. Each G5 processor has a dedicated interface to main memory for total bandwidth of up to 10 GBps per processor, or a total of 20 GBps for a quad system. This high-performance frontside bus architecture also enables each core to discover and access data in the other cores? caches?further increasing performance on quad-core systems.
It seems that's you are right for the bus thing, but the fact that the core can share the caches, is a great plus over the pentium D architecture.
At the light of the performances of the quad system compared to the dual 2,7 ghz, it seems that this architecture is not that bad.
Originally posted by PB
OK, I am not sure. I cannot find any details on the 970MP in IBM's site.
My understanding from Others In The Know in this forum was that there was one frontside bus per core - not per processor, contrary to Apple's documentation. Apple has a conflict online - the apple store says, for the 2.3: "1.15 GHz frontside bus per processor" but the tech specs page on the 2.3 just says ... "1.15 GHz frontside bus." So I gather it is one bus PER CHIP; the dual core processors can communicate directly and quickly, yes, but both have to share the same bus out to memory for the single-dual 2.3.
Originally posted by bjewett
Apple has a conflict online - the apple store says, for the 2.3: "1.15 GHz frontside bus per processor" but the tech specs page on the 2.3 just says ... "1.15 GHz frontside bus." So I gather it is one bus PER CHIP
From my understanding, yes, processor now in Apple means the chip, not the processing core.
But there is a microbenchmark available to measure cache-to-cache intervention performance (I forget whether it was on Ars or Ace's). So if interventions to the same chip are faster than to the other chip, you'll have your answer.
As for the FSB bottleneck on the 2.0 and 2.3 models, I'll wait for the STREAM numbers before deciding.
First of all, try not to use the word "processor" because to some people it means "core" and to some it means "chip". Personally I think it makes more sense that "processor = core", but I'm not going to get into that discussion.
Second, all multi-processor architectures (on or off the same chip) communicate via a bus of some kind or another. Heck, even the core communicates with its own cache via an internal bus!
Third, the two 970 cores in the 970MP chip are connected to the front side bus interface unit... which is also on the chip. The statement on Apple's page means they can send information between the two cores on the one chip via this FSBIU without having to send it down the motherboard wires to the memory controller and back again (which is what the Pentium D has to do AFAIK). Sending information between the two 1 MB caches in this way is going to be much faster than sending it off the chip, so yes this is a good thing. I don't know the details of this connection, but it is possible that it happens at the full chip clock rate and not the 1/2 speed FSB rate.
As the previous gentleman said, don't worry about it. Only somebody hardcore like me is really going to care.
Originally posted by bjewett
So I take it two i/o bound apps are going to have a cow when run on a single-dual machine like the 2.3. But one app that is multi-processor aware should do really well.
I'll ask the question - is FCP multi-processor aware?
Not at all. I/O is done on the DMA part of the companion chip and almost none of that traffic hits the CPU bus.
The FSB crossbar is the high speed connection between the caches, and it is in the part of the FSB that is on silicon, not at the opposite end on the companion chip. This design avoids shared bus memory bandwidth bottlenecks, while giving a lower latency connection to the companion core's cache (if your info was there) than you would get if you had to go all the way to RAM through the companion chip.
^^^^programmer types faster than I do!
That explains a lot. I just didn't want a Pentium D chintzy dual-core setup.