basic questions...
So I've been looking for some explainations, but can't seem to find them so maybe you could point me in the right direction or maybe enlighten me? (or is there a faq for this type of info?)
What is the difference between L2 and L3 cache and what are they respectivly?
What is Front Side Bus?
What is the difference between the various types of memory? (I have PC133 is this good or bad? What are the advantages / disadvantages). It seems as though people are always saying that memory causes huge improvments in the operation of the system. I have 768 MB but almost always have around 400-500 free even afer boosting the aps I need to use, but I have 2 800MHz processors and I keep running out of processor power (I am using mostly audio programs).
What does DDR mean?
I think I have a basic understand of computers, but I would love to be able to evaluate computers more fully. Also, I want to understand how to improve what I need improving in my system.
Also, I'm gussing most of this info is not apple specific, but more just general computer info, right?
Thanks so much for any and all info!!
joshua
What is the difference between L2 and L3 cache and what are they respectivly?
What is Front Side Bus?
What is the difference between the various types of memory? (I have PC133 is this good or bad? What are the advantages / disadvantages). It seems as though people are always saying that memory causes huge improvments in the operation of the system. I have 768 MB but almost always have around 400-500 free even afer boosting the aps I need to use, but I have 2 800MHz processors and I keep running out of processor power (I am using mostly audio programs).
What does DDR mean?
I think I have a basic understand of computers, but I would love to be able to evaluate computers more fully. Also, I want to understand how to improve what I need improving in my system.
Also, I'm gussing most of this info is not apple specific, but more just general computer info, right?
Thanks so much for any and all info!!
joshua
Comments
Front side bus is the speed of the card the processors are seated on. The speed the processors talk to each other and the system.
My vote goes for DDR (double data rate) being the best type of RAM. you have pc133 SD RAM for an apple system until of course today that was top of the line the best you could have, the pc133 stood for the speed of the RAM 133MHz. there is also Rhambus RAM witch is popular in the P4.
If you want Apple's version of what those things do for the Dual G4 systems, I'll point you to Apple's tech overview of the new Dual G4 systems. It discusses L3 cache, DDR RAM, and other features of the system:
<a href="http://www.apple.com/powermac/pdf/PowerMacG4_TO-a.pdf"; target="_blank">http://www.apple.com/powermac/pdf/PowerMacG4_TO-a.pdf</a>;
Here's a quick run down...
When the CPU execute instructions, they have to come from somewhere. This is where the Cache comes in. L1 Cache is on-dye, so it's next to the CPU, and I think it's 64k or something like that. The data that resides in the L1 Cache is the most used stuff, and if the CPU can't find it there, it goes out to L2 Cache, and L3 respectively. As you go higher in L#, it's further and further away from the CPU and closer and closer to RAM. L# increase also means that the data is less important/used less often, so it's progressively slower. If the data's not in any Cache, then the CPU goes to the RAM and even HD if it has to (ie when you open a new document). At least this is my understanding of it all...
[quote]What is Front Side Bus?<hr></blockquote>
The CPU has to communicate with more than just Cache. It needs to communicate with RAM, HD, Ethernet, etc. To do so, you can either have an "embedded processor" that can handle it all, or a "North/South bridge", a set of chips that controls the CPU's communication with other stuff on the Mobo. Problem with the 7455 chip (used in the latest tower) is that while the North Bridge can communicate with the RAM at 333MHz, the data that's received by North Bridge is sent to the the CPU at 167MHz only, due to lack of MPX+ support from Moto. It's not Apple's fault, but everyone's b!tching at Apple since they don't feel like Apple got on Moto's @ss enough since the G4 Swatooth debacle.
[quote]What is the difference between the various types of memory? (I have PC133 is this good or bad? What are the advantages / disadvantages). It seems as though people are always saying that memory causes huge improvments in the operation of the system. I have 768 MB but almost always have around 400-500 free even afer boosting the aps I need to use, but I have 2 800MHz processors and I keep running out of processor power (I am using mostly audio programs).
What does DDR mean?<hr></blockquote>
Different types of memory can send data to the North Bridge at different speed. DDR = Double Data Rate, and works by sending data at both Rising and Lowering edge of the clock (determined by the bus frequency). These are the types of RAM used in the new Power Macs. So the new bus runs at 167MHz, DDR RAM can send data at 333 MHz while Single Pumped RAM can only send data at 167MHz. (PC133 is Single Pump) As mentioned above, the speed between North Bridge and CPU is NOT DDR, thus the CPU can fetch more instructions from RAM than it can handle. Just a side note, while DDR offers 2x speed in theory, just like 2 CPUs can't be utilized to 100% efficiency, DDR can't do 2x speed in reality, due to timing issues etc that the EE engineers have to worry 'bout.
Now, with a basic understanding of DDR and computer architecture, (hopefully I haven't confused you yet...Personally, I think it makes little sense to those who doesn't know how to read timing-diagrams of computer components...) maybe I can now answer your first question a little better. Why more RAM? Take Photoshop for example, if you load a picture file of say 5 MBs, which is pretty common, it won't fit in the L1, 2, 3 Cache, thus it has to reside in the RAM. Of course a 5MB file doesn't justify 1GB of RAM, but that's just an example. Due to the huge amount of eye-candy in OS X, CPU has to load A LOT of stuff from the RAM in many operations, thus having 256MB will be significantly better than 128MB. OS X have very good memory management capabilities, thus when your computer is sitting there, you see hardly any RAM being used...but when programs are actively running, free RAM comes in handy since more can be loaded and less the CPU have to try to find stuff in the HD. Like the example I've given, unless you do heavy photoshop and/or video editing sort of stuff that requires GB of blocks of data at a time, 512MB of RAM is really all you need to run (the current version of) OS X efficiently. Any extra RAM will only make marginal difference in daily usage.
[quote]Also, I'm gussing most of this info is not apple specific, but more just general computer info, right?<hr></blockquote>
you are correct. Only the details are Apple-Sepcific, as in how to implement the North Bridge, or how the CPU is implemented, or the HFS+ file system vs. UFS vs. Fat32 vs. NTFS...(last 2 are Windows file formats, and UFS is Unix) The other major bit of background you might need is RISC vs. CISC, so here's a brief explaination:
RISC = Reduced Instruction Set Computer
CISC = Complex Instruction Set Computer
The original Macs (680x0) and Intel are CISC Based. Since the days of PowerPC ('94), the CPUs in Macs ar RISC Based.
Differences? As the name implies, RISC means the CPU handles less instructions natively. Those instruction are stuff like Add, Subtract, AND, OR, etc, to make programs work the way they do. CISC in contrast, handles a lot more instructions natively, namely string manipulations etc. This probably leads you to wonder what's bad 'bout able to handle more instructions...To put it in simple words, RISC chips are designed that way so all instructions (except some very complex ones) take 1 cycle to decode, where as it may take a CISC CPU several cycle to decode. For example, a Divide instruction takes 2 cycles in RISC (one of the few exceptions), where as it takes like 16 or so to decode in CISC. (I'm not smart enough to know how to implement Multiply & Divide in 2 clock cycles, which is why I'm only EE in training
However, this only touches the tip of the whole RISC vs. CISC debate...CPUs are no longer "true RISC" or "true CISC", since both designs have advantages and disadvantages. For example, the "Altivec" engine in the G4 is CISC in some sense...it's a set of 162 (highly optimized) instructions for vector processing, which are very complex in nature. However, instead of breaking such instructions into like 200 smaller ones and use 200 CPU cycles, Altivec will handles them in 50 cycles for example. I'm not too keen on P4 design, but in the PC arena, Transmeta's Crusoe is a RISC based chip that emulates CISC instruction sets. AMD use something called Microcode to mix RISC and CISC stuff...While RISC based chip is still inherently faster than CISC based ones, it doesn't justify the 2x+ raw MHz difference. (another quick lesson 'bout pipelines, 64-bit chips if you are interested)
Hope that's more helpful than confusing...
Please feel free to add any more information you want..
Also, if any one has some good sources (books or web sites) for learning about computers please suggest!!
Thanks!
joshua
Different types of memory can send data to the North Bridge at different speed. DDR = Double Data Rate, and works by sending data at both Rising and Lowering edge of the clock (determined by the bus frequency). These are the types of RAM used in the new Power Macs. So the new bus runs at 167MHz, DDR RAM can send data at 333 MHz while Single Pumped RAM can only send data at 167MHz.</strong>
DDR is double data rate. The new Power Macs have a 167 MHz processor bus. It sends x amount of data at 167 MHz clock cycle. PC2700 DDR SDRAM sends 2x amount of data per 167 MHz clock cycle.
<strong>Just a side note, while DDR offers 2x speed in theory, just like 2 CPUs can't be utilized to 100% efficiency, DDR can't do 2x speed in reality, due to timing issues etc that the EE engineers have to worry 'bout.</strong>
Yes. Latency issues involving the fact that the address bus is at 133 MHz for PC2100 or 167 MHz for PC2700. That is, data doesn't transfer at 266 or 333 MHz, just that twice as much data is transfered at 133 or 167 MHz.
Yes, there are bus utilization issues that make comparisons across various computers difficult when talking about the theoretical bandwidths.
<strong>For example, the "Altivec" engine in the G4 is CISC in some sense...it's a set of 162 (highly optimized) instructions for vector processing, which are very complex in nature. However, instead of breaking such instructions into like 200 smaller ones and use 200 CPU cycles, Altivec will handles them in 50 cycles for example.</strong>
AltiVec is an SIMD execution unit. That's "single" instruction multiple data. CISC and RISC are instruction set architecture designs. Essentially the form and format of the commands - instructions - that can be given to a processor to execute.
A CISC design can have instruction that can vary from 8 bits to 128 bits, for instance. That's instruction size, not data size. A CISC design also can have instructions that do complex things that take multiple cycles to do. A CISC implementation can be fantastic for certain things, because of those higher order instructions.
A RISC design takes all that variability in instruction length and instruction complexity and reduces them to about the same size and complexity. All instructions are of the same size (32 bit in PPC), certain higher order instructions are limited. What this does is reduce the complexity and increases the modularity of a microprocessor's microarchitecture. It's execution units are simpler to design because all of the instructions are the same size, of the same varying degree of complexity, etc.
The AltiVec ISA is a RISC style architecture. It's instruction size is the same as a PPC instruction. It's functions do virtually the same thing as a PPC instruction. The only difference is that it can apply said instructions at the same time to multiple pieces of data.
In other words, AltiVec isn't about breaking instructions into smaller ones, which is the pre-eminent difference between RISC and CISC ISA designs.
<strong>I'm not too keen on P4 design, but in the PC arena, Transmeta's Crusoe is a RISC based chip that emulates CISC instruction sets. AMD use something called Microcode to mix RISC and CISC stuff...While RISC based chip is still inherently faster than CISC based ones, it doesn't justify the 2x+ raw MHz difference.</strong>
Both the AMD Athlon and P3/P4 break the CISC x86 ISA into RISC style micro-ops of equivalent size and complexity. AMD calls them RISC86 ops in fact.
The clockability of a chip (the MHz it achieves) has nothing to do with ISAs in todays world. It's the microarchitecture design and fabrication technology that drives MHz. And those techniques are fairly mundane and used by everyone in the industry.
In today's world, instruction set architectures [RISC, CISC, CRISC (the state-of-the-art terminology for today's processors0, VLIW (Crusoe and Itanium)] are meaningless. Today's processors have so many transistors that talk of RISC and CISC is meaningless. The only people who should be talking about them are compiler and assembly programmers.
That's essentially what I said...take 1/167MHz=6ns between clocks, and each clock has a rising and a falling edge...so you can send out data at effectively 333MHz (compared to single pumped RAM).
[quote]AltiVec is an SIMD execution unit. That's "single" instruction multiple data...A CISC design can have instruction that can vary from 8 bits to 128 bits, for instance. That's instruction size, not data size...All (RISC) instructions are of the same size (32 bit in PPC), certain higher order instructions are limited...The AltiVec ISA is a RISC style architecture. It's instruction size is the same as a PPC instruction. It's functions do virtually the same thing as a PPC instruction. The only difference is that it can apply said instructions at the same time to multiple pieces of data.
In other words, AltiVec isn't about breaking instructions into smaller ones, which is the pre-eminent difference between RISC and CISC ISA designs. <hr></blockquote>
crap, my stupid confusion over something (or i guess lack of understanding) made me look/feel really stoopid
k...onto more randomness...
64-bit addressing really only let you address A LOT more RAM. This is important for heavy photoshop and Cad people 'cuz they might want to load 4+ GB of data into RAM at one time, which 32-bit addressing doesn't allow you to do. Considering 167MHz DDR RAM can pump 2+GB of data/sec, compared to 320MB theoretical for RAID5 SCSI, it's much faster...As for the issue of "loading data from HD to RAM", I believe that's handled by DMA (direct memory access), which allow it to be MUCH faster than CPU getting it from HD over the IDE bus.
Pipelines a little later, after i have my facts better sorted out
Oh yeah, I do assembly programming...so I should know RISC vs. CISC better ^_^; had to design a RISC AVR in VHDL too...but that's another story...
(correct me if i'm wrong, but in Pentium i believe:
Mov AX, 3
Mov BX, 4
ADD AX, BX
MOV CX, 5
MOV DX, 6
ADD CX, DX
is slower than
MOV AX, 3
MOV BX, 4
MOV CX, 5
MOV DX, 6
ADD AX, BX
ADD CX, DX)
[ 08-14-2002: Message edited by: evangellydonut ]</p>
That's essentially what I said...take 1/167MHz=6ns between clocks, and each clock has a rising and a falling edge...so you can send out data at effectively 333MHz (compared to single pumped RAM).</strong>
It's a long pet peeve of mine. "333 MHz" is a marketing number. It suggests that it is more than it is. A real 333 MHz bus with 333 MHz SDRAM would perform a lot better than PC2700.
For instance, the Power Mac's 167 MHz FSB with PC2700 DDR SDRAM should perform about the same as or better than a "266 MHz" FSB with PC2100 DDR SDRAM, but when talking about the numbers, 266 MHz sounds a lot better than 167 MHz FSB. It doesn't behoove us to enter in marketing speak.
[ 08-14-2002: Message edited by: THT ]</p>
[code]
------------
| G4 CPU | backside cache bus ------
| [L1] [ L2 ]|--- 250 MHz 2x64 bit ---| L3 |
------------ 4 GB/s ------
|
|
processor bus
[front side bus (FSB)]
166.67 MHz 64 bit = 1.33 GB/s
|
|
---------------------
-------- AGP bus | core logic | memory bus --------
| AGP 4x |--- 66.67 MHz 4x32 bit ---| [system controller] |--- 166.67 MHz 2x64 bit --- | PC2700 |
-------- 1.07 GB/s | [north bridge] | 2.67 GB/s --------
---------------------
| | | |
| | | ------ Firewire 0.05 GB/s
PCI bus | |
33 MHz 64 bit | --------- Ethernet 0.13 GB/s
0.266 GB/s |
| ------------ ATA/100 0.10 GB/s
------- |
| 4 PCI |--- 0.27 GB/s ---|--- [most likely] --- boot ROM
------- |
----------------
| I/O controller |
| [south bridge] |------------ ATA/66 0.07 GB/s
----------------
|
|
USB, modem, audio, Airport, EIDE (opticals), power management
</pre><hr></blockquote>
[ 08-15-2002: Message edited by: THT ]</p>
<strong>Well, since I'm anal retentive
Those ASCII art are a pain...even the code tab doesn't use fixed width fot!