My prediction was based on general purpose cores, which is a lot tougher to do than specialized cores. Specialized cores can be made very small, very high performance, but at the expense of functionality. That's all I'm saying with respect to your original response to me.
Well, consider that the Pentium 1 only had 3.1 million transistors. The "general purpose" cores you are likely to see on large multi-way core chips in the future are likely to be short pipe, in-order, with only about dual-issue per clock. Add on a SIMD unit (which is only a few million transistors), and you're looking at only 5 million transistors or so per core. 10 million with added L1 cache. So on a 300 million transistor chip (small!) you can expect about half L2 cache plus bus and on-chip network, and the other half is about 15 cores. And they are talking about a billion transistors by around 2011 at sub-45nm, so that is easily 40-80 general purpose simple SIMD-capable cores (depending on a lot of architectural decisions).
Note that these numbers are completely off the top of my head (except the Pentium's 3.1 mil), but there are so many possible designs that anything more precise is pointless. The P4 and Athlon cores are huge because of their caches, deep pipes, and out-of-order execution. Simplify that and you can fit far far more of cores in the same space. The trick is in writing software that can take advantage of them. That will be the real challenge. The hardware guys have stopped propping up the software guys, so it is time for the software world to adapt.
Well, consider that the Pentium 1 only had 3.1 million transistors. The "general purpose" cores you are likely to see on large multi-way core chips in the future are likely to be short pipe, in-order, with only about dual-issue per clock. Add on a SIMD unit (which is only a few million transistors), and you're looking at only 5 million transistors or so per core. 10 million with added L1 cache. So on a 300 million transistor chip (small!) you can expect about half L2 cache plus bus and on-chip network, and the other half is about 15 cores. And they are talking about a billion transistors by around 2011 at sub-45nm, so that is easily 40-80 general purpose simple SIMD-capable cores (depending on a lot of architectural decisions).
Note that these numbers are completely off the top of my head (except the Pentium's 3.1 mil), but there are so many possible designs that anything more precise is pointless. The P4 and Athlon cores are huge because of their caches, deep pipes, and out-of-order execution. Simplify that and you can fit far far more of cores in the same space. The trick is in writing software that can take advantage of them. That will be the real challenge. The hardware guys have stopped propping up the software guys, so it is time for the software world to adapt.
Agreed.
IMHO, getting the necessary SW tools (at the compiler and OS levels) to developers to create multi-processor (SMP (?)) applications is critical going forward.
But to be honest, I really don't know the current state-of-the-art, WRT current Intel GUI multi-processor compiler technologies.
Oh damnit it...Since im going to have my MP till atleast 2010, im going to have a wait for Quad Core. Sigh.
You guys think ill have to wait until Aple starts selling 'em, or will I be able to later on just pick one up, and slot it into my MP/Get a specialist to put it in ?
And you think Apple will make them availible from Q12007 ?
...This new usage model will challenge the industry to deliver high-speed computing performance and terabytes of bandwidth.
One of the first prototypes chips in Intel's program is the Tflops processor. Containing 80 simple cores and operating at 3.1 GHz, the goal of this experimental chip is to test interconnect strategies for moving terabytes of data from core to core and between cores and memory, according to Intel.
Unlike existing chip designs where hundreds of millions of transistors are arranged, this chip's design consists of 80 tiles laid out in an 8- by 10-block array, according to Intel.
Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data, but the silicon is not Intel x86-based processor compatible. The tile also includes a router connecting the core to an on-chip network that links all the cores to each other and gives them access to memory.
The second major part is a 20-Mbyte SRAM memory chip that is stacked on and bonded to the processor die. Stacking the die makes possible thousands of interconnects and provides more than a terabyte-per-second of bandwidth between memory and the cores, according to Intel.
The third product is the recently announced hybrid silicon laser chip developed in collaboration with researchers at University of California at Santa Barbara. This could lead to a terabit-per-second optical link capable of speeding terabytes of data between chips inside computers, between PCs and between servers inside data centers.
I can see the last two products surfacing before the first one.
Originally Posted by 132GHz,4TB DDR8 SDRAM,95TB HDD
Hahahaha
Oh damnit it...Since im going to have my MP till atleast 2010, im going to have a wait for Quad Core. Sigh.
You guys think ill have to wait until Aple starts selling 'em, or will I be able to later on just pick one up, and slot it into my MP/Get a specialist to put it in ?
And you think Apple will make them availible from Q12007 ?
You can get eight cores in your Mac Pro. Today or in a few months(?) when Clovertown hits the shelves:
Don't forget [shitfting] software paradigms in coding for [multicore] GPUs as well...!
Yes, one hopes that some of the same new software techniques for multi-core CPUs apply to GPUs as well. Unfortunately for GPUs their execution model is less general purpose than CPUs so they simply cannot do some things as efficiently as an 80 core monster might. On the other hand, they are likely to have some advantages of their own. The big problem is that right now programming each device is done differently and in some awkward fashion, not in anything approaching a "standard" fashion. There have been a couple of recent announcements of attempts to change this, but they are all pretty niche currently.
Intel's chips sets are still behind Nvidia and Ati. The best that Intel has is x8 x8 or x1 x16 while Nvidia has x16 x16 one 590 board even has x16 x8 x16 and most 590 boards have with duel gig-e with ip/tpc offload. These are for amd 590 as the Intel ones are not out yet.
This also shows up in the workstation / severs chips sets as well. Aka the power Mac g5 has more pci-e lanes then the Mac pro and it has less bandwidth in the chip set to chip set link.
Also looking at Motherboards form super micro
Dual AMD® Opteron(TM) 2000 Series (Socket F) Support, 1000 MHz HyperTransport Link
I know we're (well, I am) sliding into PC Gaming land but the reference to High-End Graphics Xeon Workstation stands. Nonetheless I don't know if one badass Quadro is good enough. Or two medium-ass or two badass Quadros SLI'ed is even better. Or if the Quadroplex is really a feasible/ good option for a high-end-workstation setup??
I know we're (well, I am) sliding into PC Gaming land but the reference to High-End Graphics Xeon Workstation stands. Nonetheless I don't know if one badass Quadro is good enough. Or two medium-ass or two badass Quadros SLI'ed is even better. Or if the Quadroplex is really a feasible/ good option for a high-end-workstation setup??
there are alot Xeon Workstation boards that don't even have a full x16 slot they only run it x8 some only have x8 slots
there are alot Xeon Workstation boards that don't even have a full x16 slot they only run it x8 some only have x8 slots
That's because most Xeons are not used for purposes that require a 16 lane board running at full speed ahead. They will accept the physical 16 lane board, but only let run with four.
Apple does the same thing. All of its slots will fit a 16 lane board, but only one will run in 16 lanes.
That's because most Xeons are not used for purposes that require a 16 lane board running at full speed ahead. They will accept the physical 16 lane board, but only let run with four.
Apple does the same thing. All of its slots will fit a 16 lane board, but only one will run in 16 lanes.
so people who do high end 3d work use amd systems.
so people who do high end 3d work use amd systems.
High-end 3D work uses an incredibly small amount of bandwidth, even in an unoptimized program.
16-lanes is really only useful for quick scene changes where there's lots of texture changes, or situations where you have too many textures and not enough VRAM, and caching isn't as efficient. In other words, games.
so people who do high end 3d work use amd systems.
No. That has nothing to do with it. AMD mobo's are the same. It's up to the machine manufacturer to decide what they want to put on the board, not the chip manufacturer. They both allow for enough lanes.
Comments
My prediction was based on general purpose cores, which is a lot tougher to do than specialized cores. Specialized cores can be made very small, very high performance, but at the expense of functionality. That's all I'm saying with respect to your original response to me.
Well, consider that the Pentium 1 only had 3.1 million transistors. The "general purpose" cores you are likely to see on large multi-way core chips in the future are likely to be short pipe, in-order, with only about dual-issue per clock. Add on a SIMD unit (which is only a few million transistors), and you're looking at only 5 million transistors or so per core. 10 million with added L1 cache. So on a 300 million transistor chip (small!) you can expect about half L2 cache plus bus and on-chip network, and the other half is about 15 cores. And they are talking about a billion transistors by around 2011 at sub-45nm, so that is easily 40-80 general purpose simple SIMD-capable cores (depending on a lot of architectural decisions).
Note that these numbers are completely off the top of my head (except the Pentium's 3.1 mil), but there are so many possible designs that anything more precise is pointless. The P4 and Athlon cores are huge because of their caches, deep pipes, and out-of-order execution. Simplify that and you can fit far far more of cores in the same space. The trick is in writing software that can take advantage of them. That will be the real challenge. The hardware guys have stopped propping up the software guys, so it is time for the software world to adapt.
Well, consider that the Pentium 1 only had 3.1 million transistors. The "general purpose" cores you are likely to see on large multi-way core chips in the future are likely to be short pipe, in-order, with only about dual-issue per clock. Add on a SIMD unit (which is only a few million transistors), and you're looking at only 5 million transistors or so per core. 10 million with added L1 cache. So on a 300 million transistor chip (small!) you can expect about half L2 cache plus bus and on-chip network, and the other half is about 15 cores. And they are talking about a billion transistors by around 2011 at sub-45nm, so that is easily 40-80 general purpose simple SIMD-capable cores (depending on a lot of architectural decisions).
Note that these numbers are completely off the top of my head (except the Pentium's 3.1 mil), but there are so many possible designs that anything more precise is pointless. The P4 and Athlon cores are huge because of their caches, deep pipes, and out-of-order execution. Simplify that and you can fit far far more of cores in the same space. The trick is in writing software that can take advantage of them. That will be the real challenge. The hardware guys have stopped propping up the software guys, so it is time for the software world to adapt.
Agreed.
IMHO, getting the necessary SW tools (at the compiler and OS levels) to developers to create multi-processor (SMP (?)) applications is critical going forward.
But to be honest, I really don't know the current state-of-the-art, WRT current Intel GUI multi-processor compiler technologies.
Oh damnit it...Since im going to have my MP till atleast 2010, im going to have a wait for Quad Core. Sigh.
You guys think ill have to wait until Aple starts selling 'em, or will I be able to later on just pick one up, and slot it into my MP/Get a specialist to put it in ?
And you think Apple will make them availible from Q12007 ?
http://www.eetimes.com/news/latest/s...leID=193005741
...This new usage model will challenge the industry to deliver high-speed computing performance and terabytes of bandwidth.
One of the first prototypes chips in Intel's program is the Tflops processor. Containing 80 simple cores and operating at 3.1 GHz, the goal of this experimental chip is to test interconnect strategies for moving terabytes of data from core to core and between cores and memory, according to Intel.
Unlike existing chip designs where hundreds of millions of transistors are arranged, this chip's design consists of 80 tiles laid out in an 8- by 10-block array, according to Intel.
Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data, but the silicon is not Intel x86-based processor compatible. The tile also includes a router connecting the core to an on-chip network that links all the cores to each other and gives them access to memory.
The second major part is a 20-Mbyte SRAM memory chip that is stacked on and bonded to the processor die. Stacking the die makes possible thousands of interconnects and provides more than a terabyte-per-second of bandwidth between memory and the cores, according to Intel.
The third product is the recently announced hybrid silicon laser chip developed in collaboration with researchers at University of California at Santa Barbara. This could lead to a terabit-per-second optical link capable of speeding terabytes of data between chips inside computers, between PCs and between servers inside data centers.
I can see the last two products surfacing before the first one.
Hahahaha
Oh damnit it...Since im going to have my MP till atleast 2010, im going to have a wait for Quad Core. Sigh.
You guys think ill have to wait until Aple starts selling 'em, or will I be able to later on just pick one up, and slot it into my MP/Get a specialist to put it in ?
And you think Apple will make them availible from Q12007 ?
http://arstechnica.com/journals/appl...2006/9/13/5275
http://techfreep.com/eight-core-mac-...clovertown.htm
http://www.anandtech.com/printarticle.aspx?i=2832
Thank you very much !
Don't forget [shitfting] software paradigms in coding for [multicore] GPUs as well...!
Yes, one hopes that some of the same new software techniques for multi-core CPUs apply to GPUs as well. Unfortunately for GPUs their execution model is less general purpose than CPUs so they simply cannot do some things as efficiently as an 80 core monster might. On the other hand, they are likely to have some advantages of their own. The big problem is that right now programming each device is done differently and in some awkward fashion, not in anything approaching a "standard" fashion. There have been a couple of recent announcements of attempts to change this, but they are all pretty niche currently.
This also shows up in the workstation / severs chips sets as well. Aka the power Mac g5 has more pci-e lanes then the Mac pro and it has less bandwidth in the chip set to chip set link.
Also looking at Motherboards form super micro
Dual AMD® Opteron(TM) 2000 Series (Socket F) Support, 1000 MHz HyperTransport Link
2 (x16), 1 ( x8 ), 1 (x4) PCI-e, 1 64-bit 133MHz PCI-X, 1 64-bit 100MHz PCI-X
Up to 16GB DDR2 667 SDRAM (or)
Up to 16GB DDR2 533 SDRAM (or)
Up to 32GB DDR2 400 SDRAM
Dual-port Gigabit LAN/Ethernet Controller
2-Channel Ultra320 SCSI with Zero-Channel RAID support
Dual Intel® 64-bit Xeon® Support (667 / 1066 / 1333MHz FSB)
Up to 32GB DDR2 667 & 533MHz FB-DIMM
1(x16) & 1(x4 in x16) PCI-E, 2 64-bit 133MHz & 1 64-bit 100MHz
PCI-X, 1 32-bit PCI
Dual-Channel Ultra320 SCSI & Zero-Channel RAID Support
Dual-port Gbit LAN
The amd board has a lot more pci-e slots
Tyan
(2) AMD Opteron(TM) (Rev.F) 2000 series processor support (1207-pin)
( 8 ) DDR2 DIMMs sockets; up to 32GB reg. DDR2 400/533/667 mem.
Supports ECC memory moduels; dual channel memory bus
(4) PCI-E x16 slots
- (1) x16 signal from IO55
- (1) x16 from MCP55
- (1) x16 from MCP55 with x8 signal
- (1) x16 from IO55 with x8 signal
(2) PCI-X 100MHz slots from NEC nPD720404
or (1) PCI-X 133MHz slot if 133MHz card is used
(1) PCI v2.3 32-bit 33MHz slot
(7) Expansion slots total
(6) SATA2 ports (3.0Gb/s), ( 8 ) SAS ports (opt.), and (2) GbE LAN ports
(1) 1394a FireWire port and integrated audio
SSI/Extended ATX footprint (13" x 12"; 330.2mm x 304.8mm)
Tyan does not any xeon workstation board with a full x16 slot.
To running something like this http://www.nvidia.com/page/quadroplex.html [nvidia.com] at the max you need 2 full x16 links.
http://www.nvidia.com/page/nforce_pro_workstation. html [nvidia.com]
intel is missing out on the high end workstation graphics market.
But I don't know why it says Dual PCIe-x16 when the specs are written as such:
1. 2 x PCI Express X16 slot(x16, x4)
2. 3 x PCI Express X1 slots
3. 2 x PCI slots
For Conroe/Allendale Intel Core 2 Duo desktops (mid-to-high-end gaming/ mid-end workstation) the Gigabyte board is highly recommended: http://www.gigabyte.com.tw/Products/...me=GA-965P-DQ6
But I don't know why it says Dual PCIe-x16 when the specs are written as such:
1. 2 x PCI Express X16 slot(x16, x4)
2. 3 x PCI Express X1 slots
3. 2 x PCI slots
Edit: Yes it corroborates with above specs for Xeon chipset:
Dual Intel® 64-bit Xeon® Support (667 / 1066 / 1333MHz FSB)
Up to 32GB DDR2 667 & 533MHz FB-DIMM
1(x16) & 1(x4 in x16) PCI-E, 2 64-bit 133MHz & 1 64-bit 100MHz
PCI-X, 1 32-bit PCI
It operates at x16 and x4 for the two PCI-E slots. Can it run x8 x8 SLI with the drivers that allow SLI on non-nVidia-SLI-chipsets? Hmm...
I know we're (well, I am) sliding into PC Gaming land but the reference to High-End Graphics Xeon Workstation stands. Nonetheless I don't know if one badass Quadro is good enough. Or two medium-ass or two badass Quadros SLI'ed is even better. Or if the Quadroplex is really a feasible/ good option for a high-end-workstation setup??
there are alot Xeon Workstation boards that don't even have a full x16 slot they only run it x8 some only have x8 slots
there are alot Xeon Workstation boards that don't even have a full x16 slot they only run it x8 some only have x8 slots
That's because most Xeons are not used for purposes that require a 16 lane board running at full speed ahead. They will accept the physical 16 lane board, but only let run with four.
Apple does the same thing. All of its slots will fit a 16 lane board, but only one will run in 16 lanes.
That's because most Xeons are not used for purposes that require a 16 lane board running at full speed ahead. They will accept the physical 16 lane board, but only let run with four.
Apple does the same thing. All of its slots will fit a 16 lane board, but only one will run in 16 lanes.
so people who do high end 3d work use amd systems.
so people who do high end 3d work use amd systems.
High-end 3D work uses an incredibly small amount of bandwidth, even in an unoptimized program.
16-lanes is really only useful for quick scene changes where there's lots of texture changes, or situations where you have too many textures and not enough VRAM, and caching isn't as efficient. In other words, games.
so people who do high end 3d work use amd systems.
No. That has nothing to do with it. AMD mobo's are the same. It's up to the machine manufacturer to decide what they want to put on the board, not the chip manufacturer. They both allow for enough lanes.