DDR Compatibility with the G4 (from Mot)

Posted:
in Future Apple Hardware edited January 2014
got this from Mot's FAQ section



question 1

[quote]1/26/2001 - I'm curious, I E-mailed you recently asking if there would be a significant performance gain going from PC133 to DDR. I somehow relayed the information to a person on a message board which immediately started a huge thread war over the issue. I should have been more specific and asked if DDR SDRAM would improve performance significantly in a MP configuration. Anyway, here is the person's assessment of the situation. It's quite thorough. [[[[Ok, whatever Apple wants to call it doesn't matter, but the question of whether Apple has DRR (gawd help us if they went RDRAM) in the works and when it might mature remains very relevant. Here is a post copied from a thread below (the whole thread is amusing) which appears to set out the issues, and particularly rebuts the notion various "Applepologists" have been advancing that the G4s CAN'T do DDR ... which isn't true. This author makes the point that you don't need DDR if you don't use MP and you don't use Altivec ... but I WANT TO DO MP ALTIVEC ... and I need more memory bandwidth! *************** Clarification of facts Posted By: Cincinatus Date: 25-Jan-2001 1:11 p.m. In Response To: Trying to (Ed M.) I normally do not follow posts at places like Macweek; this was brought to my attention by a friend who asked me for a technical opinion over whether the MPC7410 (G4) and MPC7450 ("G4+") can support DDR, and secondarily whether it is useful to do so. Protecting the reputation of Motorola's G4 series is important to me and my business, and so I will answer this question in print here. Unfortunately Ed's use of a quote which is literally (but narrowly) correct, yet misleading in the context he presents it, provides a perfect example of why it is foolish for any company to be identified as a "source." Hence I will not identify myself or my company, and will instead adopt an ars-technica-like alias. I want anyone reading this to judge it solely on the material presented anyway. I specifically wish to address the technical implications of the following claim Ed makes about a statement "from a person at Motorola." Anyone following the thread will note that this statement was originally attributed to "an engineer at Motorola" and is now attributed to "a person at Motorola," and let me simply say first that either such attribution cannot be taken to imply any endorsement of this statement by Motorola whatsoever, but again that the statement is _literally_ correct, but does not address the point for which Ed attempts to use it. [[[[ quote from Ed ]]] Never said that it was impossible. I simply posed a question to a a person at Moto. asking him how much of a performance increase could be expected with DDR. As a matter of fact, here is the exact question: ***How limited is the new G4 7450's with respect to memory bandwidth on PC133? How is the new chip designed to deal with such obstacles and will the use of DDR-SDRAM improve the performance significantly?*** His answer: ***Ultimately, with the processor bus is running at 133Mhz, even if you use a memory controller which utilizes the double data rate (both rising and falling edge), the processor only reads or writes on the rising edge. Thus limiting your memory bandwidth to 133MHz and not improving the performance significantly.*** [[[ end of quote from Ed ]]] Now there is some fractured grammar over "with the proccesor bus is running... but let me restate what is said here simply: "If the MPX processor bus is running at 133 MHz there is no advantage to DDR." True statement. But the G4 MPX bus need not run at 133 MHz. Now let me quote from a previous post by Lee: [[[quote from Lee The MPX bus can be run at any fixed integer sub-rate of the clock from 2 on up (meaning that if 2 then every CPU opportunity has an available memory fetch .. otherwise the CPU waits till satisfied) Now if we are using DDR where data are fetched on two edges of the clock, then consider P1600 DDR (the slower of the two DDR right now, effectively 2x PC100) then there are 200 Mops to the memory, and a 400 MHz G4 would be the minimum-speed processor which theoretically could use every one. NO PROBLEMO! In reality due to caching etc no CPU would use all the cycles, so two processors could share a bus pretty effectively. G4 synch speeds for PC1600 would go 400, 600, 800 ... etc (rather than by 100s for SDRAM) but this is not really a problem. Further the arithmetic for PC2100 (the faster DDR which is effectively 2x PC133) would go 533 MHz and then up by increments of 266. What that means is that TODAY the older MPC7410 can be used quite nicely with either PC1600 or PC2100, presuming you have a "uni-north" equivalent for DDR at 400 or 533 MHz respectively ..... although DDR would not provide substantial performance gain for this CPU *except* in MP configurations. end quote ]]] This explains the most basic elements of the timing. Restating the consequences again hoping to make this very clear, a 533 MHz G4 (MPC7410 e.g.) running with PC133 memory uses a clock ratio of 4 for its MPX bus rate to achieve the 133 MHz needed. This is current practice in the new Macintosh computers. The previous models which used PC100 and ran at 500 MHz used a clock ratio of 5 to get the 100 MHz needed. However 4 is not the lowest clock ratio permitted; A 533 MHz G4+ using PC2100 (2 x 133 DDR) would use a ratio of 2 for its MPX bus rate to achieve the 266 MHz needed. There is no problem with the MPX bus. However any G4 design migrating from SDRAM (PC100, PC133) to DDR needs a substantially different memory interface controller (aka "northbridge" in PC parlance) to handle DDR. This is in contrast to the effort needed to move from PC100 to PC133, where the signal and interface formats are identical; the second only requires a higher speed. There are no fundamental difficulties in building a DDR interface, but it is a significant R&D effort. I have no information as to whether Apple has an effort of this kind in progress (as has been extensively rumored) or even intends to develop such an item. While this is the end of the limited clarification of facts that I wanted to communicate, a further issue of some practical consequence is whether shifting to DDR will provide significant performance benefit. Here the situation becomes much more complex to analyze because it depends very sensitively on the design of the memory interface, processor and cache configurations, and the algorithm in question at the machine language level (This means that in many cases the specifie compiler optimization (or lack there of) performed maters!) Readers should be extremely wary of seeing some "fact" taken from this or that comparison or test, and generalizing it inappropriately. Interested readers may wish to see <a href="http://www4.tomshardware.com/mainboard/01q1/010124/index.html"; target="_blank">http://www4.tomshardware.com/mainboard/01q1/010124/index.html</a>; which shows that 1 GHz Athon systems with recently introduced DDR memory have achieved very modest performance gains (0 to 10%) over PC133 for a range of algorithms tested on two systems with differing memory, and that 1 GHz Pentium chips have lower performance running with an i820 memory controller and various RDRAM ("rambus") configurations. These tests demonstrate real-world performance to users, and make it clear that users should not automatically expect significant improvements over PC133 solutions from these more advanced memories. Without going into the complexities of the issues here, the implementions of both of these early advanced-memory systems did not use the respective memories to best advantage, and neither should be taken as some sort of broader defining statement about DDR or RDRAM. (On the otherhand if you are considering buying these particular systems the tests show you very clearly not to waste your money on the "fancier memory.") While the prose at Tom's Hardware is a bit florid, I will go so far as to agree to the sentiment expressed that the Pentium3-i820-RDRAM combination was ill-advised from conception, and driven more by Rambus marketing needs than any engineering utility. Now with respect to the G4 and the G4+, and in an attempt to keep things simple, most SINGLE CPU algorithms, NOT USING ALTIVEC, will get only a small advantage from DDR over PC133. This will be true even for the 733 MHz MPC75450, which will have performance for these algorithms comparable to the 1 GHz P3 or Athlon as tested. However, in multi-processor configurations, or Altivec algorithms running on data too large to fit into cache, memory bandwidth requirements are very substantially increased, and DDR properly implemented would yield substantial gain. As Altivec and MP computing are important to Apple, I believe it will be necessary for Apple to progress to DDR or RDRAM before dual-CPU 733 MHz systems are released. ]]] end quote.Any additional information that you may be able to provide will be greatly appreciated.<hr></blockquote>



response 1

[quote]1/29/2001 - CJC -



One premise in this treatise bothers me. The author implies that the bus frequency is arbitrarily determined ("The MPX bus can be run at any fixed integer sub-rate of the clock from 2 on up"). Actually, the reverse is true.



The bus frequency is limited by the very practical considerations of output valid, input set-up, and time-of-flight. Our hardware specifications give a maximum bus frequency of 133 MHz because that's the upper limit of practical operation given the output valid, input set-up, and an assumed time-of-flight in the customer's application.



The core frequency can then be any integer or half-integer multiple of the bus frequency (from the list of multiples supported by the PLL) up to the maximum frequency marked on the top of the part (slightly below where the part malfunctions due to internal timing constraints).



Remember the old quote "Time is what keeps everything from happening simultaneously?" Well, propagation delays in the real world set the upper limit on frequencies of operation, internal and external.



WRT the overall question: I would expect performance improvements in systems where the memory controller (North Bridge in the email track) can support DDR. The goal is to minimize time between the request for data and return of data. After the first access in an four double-word burst, DDR SDRAMs are going to return data to the memory controller at a faster pace than standard SDRAMs. Even the non-dual data rate MPX bus can potentially benefit by having less dead cycles between beats (returned by the memory controller) in a burst or between bursts (initiated by the same or another processor) if the memory controller has the data in its buffers sooner.



The MPX bus devotes a lot of its protocol to improving bus utilization by allowing data streaming (fast back-to-back transfers), pipelined transfers (separate address and data tenures to allow multiple slave devices, i.e. memory, to overlap their access times), and out-of-order transactions (to allow fast slave devices to bypass slower slave devices). <hr></blockquote>



question 2

[quote]2/7/2001 - My questions will be as straight forward as possible. Numerous discussionson various "message boards" have been centering on DDR-SDRAM and whether ornot a "significant" performance gain would be evident if it were used withthe new PPC 7450 microprocessor instead of the current PC 133 offering. Thequestions are as follows:1: Given the "appropriate memory controller", would the use of DDR improveperformance significantly? What percentage increase coud we expect?2: More specifically, how would DDR-SDRAM affect the performance of a systemwith 2 or more PPC 7450's running in parallel?<hr></blockquote>



response 2

[quote]I can only give generic answers to the questions below.



I am assuming that the DDR-SDRAM is running at a 266 MHz data rate, 64-bits wide, and the MPX bus on the MPC7450 is running at 133MHz 64-bits wide. In this scenario, the bandwidth of the SDRAM is higher than the bandwidth of the MPX bus. This means that no additional bandwidth can be seen by the processor. However, in a typical system there are multiple requestors of main memory (processor, graphics, I/O). All of this vie for bandwidth at main memory at an arbitration point inside the north bridge chip. If the bandwidth of main memory is doubled, then performance of the system will go up due to less blocking at the memory controller. This means that overall achievable system bandwidth is higher and latency from one requestor to memory will be less when requests from multiple sources happen simultaneously.



The amount of system performance increase is highly dependent on the specific

system workload.



<hr></blockquote>





So, from what I take the 7450 does not support DDR.

:confused: is that right?



will "Apollo" be a big enough change to change that. Mot makes it sound like its a limitation of the MPX Bus



[ 01-22-2002: Message edited by: applenut ]</p>
«13

Comments

  • Reply 1 of 46
    Did anybody read all of that?

    :eek:
  • Reply 2 of 46
    bodhibodhi Posts: 1,424member
    What in the hell was that?



    Who was asking the questions? Who was answering them? Man, after reading that I have no idea where I am right now...all disoriented?!? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
  • Reply 3 of 46
    msleemslee Posts: 143member
    Fascinating stuff, applenut.



    From what I've gathered, the G4+ can benefit from DDR SDRAM in the situations listed above: namely in dual processor configurations where two animals are feeding at the trough and when the cache(s) are being emptied faster than they can be filled.



    Currently, the memory controller on the G4+ does not support DDR SDRAM
  • Reply 4 of 46
    applenutapplenut Posts: 5,768member
    [quote]Originally posted by Bodhi:

    <strong>What in the hell was that?



    Who was asking the questions? Who was answering them? Man, after reading that I have no idea where I am right now...all disoriented?!? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> </strong><hr></blockquote>



    I spent a litle time in the computer lab after school going through Mot's website and found some cool stuff, one of which is above.



    the responses are all one really needs to read to get an understanding of the main topic
  • Reply 5 of 46
    amorphamorph Posts: 7,112member
    It's not possible to link directly to the document applenut is referencing, but here are directions:



    1) Go to <a href="http://e-www.motorola.com"; target="_blank">http://e-www.motorola.com</a>;



    2) Under "Technical Support and Contacts," in the lower right-hand corner of the front page, there's a FAQ link. Click it.



    3) Under the search box, you'll see a table listing processors. Under "32 bit processors" -&gt; "PowerPC Architecture" you'll see "MPC7xxx". Click that.



    4) Another search page will come up. In the uppermost dropdown menu, find and select "MPC7450 (V'Ger)". Leave the other fields alone. Click Search.



    5) You'll get a page with problem/solution pairs, set up like a bulletin board. Scroll down a bit to see the posts applenut is quoting. They're a bit easier to comprehend once you can see which are questions and which are answers.



    As far as I can discern, this all means that the 7450 - and more broadly, the MPX bus - don't support clock doubling, although a system built around a 7450 (or, in particular, more than one 7450) could still benefit in certain applications from DDR RAM.



    [ 01-22-2002: Message edited by: Amorph ]</p>
  • Reply 6 of 46
    I was amused by the reference to "ars-technica like aliases". I presume he means like Ken "Caesar" Fisher and John "Hannibal" Stokes...



    Ok, so no DDR with current systems. However, I cannot conceive of Apple not implementing DDR, RDRAM or some other advanced memory technology if there are more in their next desktop.
  • Reply 7 of 46
    thttht Posts: 3,249member
    <strong>Originally posted by Amorph:

    As far as I can discern, this all means that the 7450 - and more broadly, the MPX bus - don't support clock doubling, although a system built around a 7450 (or, in particular, more than one 7450) could still benefit in certain applications from DDR RAM.</strong>



    Ding ding ding! Though the latter part is getting more wrong due to increasing processor clock rate. The comments were written when DRDRAM and DDR SDRAM just came out in late 2000.



    It's very simple. Yet, there's like a million monkeys typing away out there in the Datasphere and no one's put out some Shakespeare yet. Sheesh.



    In today's PC architectures, what was known as the system bus, the pathway from memory to processor, can be broken up into two: a memory-to-memory-controller bus and a memory-controller-to-processor bus. In G4 Macs, this memory-controller-to-processor bus is called the MPX bus (Maxbus). For lack of a fancier term, the memory-to-memory-controller bus is the memory bus. The MPX bus at 64 bit 133 MHz can has 1067 MByte/s of theoretical throughput. The G4 Mac 64 bit 133 MHz memory bus has 1067 MByte/s theoretical throughput. This is the way it should be done and there are no bottlenecks.



    PC2100 DDR SDRAM has 2100 MByte/s of theoretical througput. So if Apple puts DDR SDRAM into G4 Macs, we have a 2100 MByte/s memory bus pushing data through a 1067 MByte/s MPX processor bus. Bottleneck. There is really no use in putting DDR SDRAM until Motorola supports DDR transfers in the MPX bus. Maybe it will be there with the Apollo G4, who knows.



    With everything balanced, PC2100 DDR SDRAM will only give an approximate 10% boost in performance and it's more likely 5% over PC133. The problem hindering it compared to PC133 is latency due to the address bus only operating at 133 MHz. Ie, only transfers addresses once per clock cycle. The theoretical doubling of throughput is never ever realized. PC2100 will give about 600 to 700 MHyte/s of real world memory performance.



    DRDRAM, Rambus, is getting a bad reputation due to Rambus, Inc's legal policies. As a technology however, I prefer it over DDR SDRAM. It offers nearly twice as much throughput and with low pin count, multiple channels can be utilized to double or quadruple throughput. A quad short channel Rambus L3 cache design would be vary nifty. For AltiVec and Apple's sorts of programs (streaming multimedia), DRDRAM would be excellent.
  • Reply 8 of 46
    Edit:



    I posted this before THT's take, so I'm not sure this is truly valid, but I'm interested enough to have someone knowledgable take it apart.



    -------



    I wouldn't take it to say that the G4/G4+ cannot support DDR SDRAM, but that the key is 1) if the system is DP and 2) if the application is using Altivec. Given 1+2, then the real question is whether or not the data is too large to sit within the cache's of the chips. If the data is large, then DDR SDRAM will make a significant difference.



    OK, so what applications use altivec, make use of MP and use large chunks of memory? How about Video, Audio and everything else the Digital Hub deals with.



    I would imagine that applications like iDVD, iMovie, iTunes, FCP et al. would benefit immensely from this. However, it is more of a mobo change than a processor change, again an issue with Apple.



    I also could see how some serious kernal level work could make the implementation of DDR SDRAM really applicable to a number of OS X features. However, this sounds like a huge amount of work with the software and hardware folks perhaps working closer than they have in the past.



    [ 01-22-2002: Message edited by: Mac Glue Sniffer ]</p>
  • Reply 9 of 46
    amorphamorph Posts: 7,112member
    THT wrote:



    [lots of good stuff, including:]



    [quote]<strong>In today's PC architectures, what was known as the system bus, the pathway from memory to processor, can be broken up into two: a memory-to-memory-controller bus and a memory-controller-to-processor bus. In G4 Macs, this memory-controller-to-processor bus is called the MPX bus (Maxbus). For lack of a fancier term, the memory-to-memory-controller bus is the memory bus. The MPX bus at 64 bit 133 MHz can has 1067 MByte/s of theoretical throughput. The G4 Mac 64 bit 133 MHz memory bus has 1067 MByte/s theoretical throughput. This is the way it should be done and there are no bottlenecks.



    PC2100 DDR SDRAM has 2100 MByte/s of theoretical througput. So if Apple puts DDR SDRAM into G4 Macs, we have a 2100 MByte/s memory bus pushing data through a 1067 MByte/s MPX processor bus. Bottleneck. There is really no use in putting DDR SDRAM until Motorola supports DDR transfers in the MPX bus. Maybe it will be there with the Apollo G4, who knows.</strong><hr></blockquote>



    Interesting.



    Particularly in light of the rumor that the G5 will feature an on-die memory controller. Assuming for the sake of discussion that this is true, the CPU should have a much fatter pipe to the memory controller - that being the point of putting the controller on die, as far as I can tell - and then the only potential bottleneck becomes the bus to memory. Correct?



    Again given the above, how would an MP G5 configuration work? Does the presence of multiple memory controllers significantly complicate SMP?



    Thanks for helping to clear things up.
  • Reply 10 of 46
    programmerprogrammer Posts: 3,409member
    All this talk about MP systems being able to take advantage of DDR misses an important point... the memory controller only has one MPX bus coming out of it, regardless of how many G4s are in the machine. All G4s sit on the same MPX bus and "snoop" eachother's activity to make sure they don't step on eachother's toes. This means that their combined throughput is limited to the throughput of the one MPX bus -- roughly 1 Gb/sec.



    It would be possible, but rather complicated and expensive, to build a memory controller (and motherboard) that had multiple MPX busses... but Apple is unlikely to do it. The more traces you have to put on a motherboard, the harder it gets to build due to interference between the lines and arranging all the darn things. An MPX bus needs a large number of lines (128 at least, I think), so two of them requires twice as many traces. Yuck. This is the kind of thing IBM, Sun and SGI do in their high-end machines, and part of the reason they are expensive. So I don't think we'll see it happen.



    Its possible that Motorola will definied a clock doubled MPX bus, or a faster one, or a 128-bit one (I think the 128-bit one is already defined) - but if that shows up in a Mac then I'd guess that the G5 is a long way off. If you think the G5 is close then I don't think we'll see Apple wasting effort getting DDR working with the G4.



    The G5 is supposed to have either HyperTransport or RapidIO. The idea here is to have many fewer lines (reducing interference), but at a much higher clock rate. This is along the same lines as RAMBus' memory interface.





    Having seen some of my code run on both DDR and RamBus equipped machines, I must say that I prefer DDR... at least at the current technology levels. RamBus tends to have very poor latency, much worse than DDR. For non-media processing code the latency is very painful and DDR suffers less. In my experience there isn't much to choose between RamBus and DDR when doing media processing work (i.e. running sequentially through large data sets), but both are much faster than SDRAM. I've seen some algorithms run almost twice as fast. Add RamBus' politics into the equation and I'd be happy if they curled up and died. Intel seems to be feeling the same way lately.
  • Reply 11 of 46
    programmerprogrammer Posts: 3,409member
    [quote]Originally posted by Amorph:

    <strong>THT wrote:

    Again given the above, how would an MP G5 configuration work? Does the presence of multiple memory controllers significantly complicate SMP?

    </strong><hr></blockquote>





    Yes. It should be doable though. A multi-core G5 would be much happier, however, since it could then keep all the interactions on-chip.



    (not that I expect to see that for a while)
  • Reply 12 of 46
    thttht Posts: 3,249member
    <strong>Originally posted by Amorph:

    that being the point of putting the controller on die, as far as I can tell - and then the only potential bottleneck becomes the bus to memory. Correct?</strong>



    Yes. Unless of course the on-die memory controller only supports a certain type of RAM



    <strong>Again given the above, how would an MP G5 configuration work? Does the presence of multiple memory controllers significantly complicate SMP?</strong>



    Not really. Just look up NUMA (non-uniform memory architecture) at google. The basic architecture is processors connected through a RapidIO or HyperTransport bus with hopefully a non-blocking cross bar switch to bridge them. RapidIO or HyperTransport would have 2 to 4 GByte/s of throughput at 500 MHz. This is the basic architecture used for most of the 16, 32, 64, 128 processor machines sold today. It's not a shared memory bus seen in most SMP systems.



    Problem is multi-processor machines will always be specialist machines. So, I'm not sure it's a very relevant question. I suppose Apple could set a trend with a dual-processor iMac, but it would be up to Moto selling a G4 for 50$.
  • Reply 13 of 46
    outsideroutsider Posts: 6,008member
    The 133MHz system bus 'limit' on the 7450 is more of a guideline than anything. For example it was possible to modify the bus speed of a B&W G3 to 120MHz or even 133MHz by rearranging some dip switches. But the official limit was 100MHz. If the northbridge and motherboard was properly designed, how difficult would it be to impliment a 64bit (or even 32bit) 266MHz bus? I think if the NB was kept VERY close to the processor (say on the underside of the daughter card) it would be possible.
  • Reply 14 of 46
    [quote]Originally posted by Outsider:

    <strong>The 133MHz system bus 'limit' on the 7450 is more of a guideline than anything. For example it was possible to modify the bus speed of a B&W G3 to 120MHz or even 133MHz by rearranging some dip switches. But the official limit was 100MHz. If the northbridge and motherboard was properly designed, how difficult would it be to impliment a 64bit (or even 32bit) 266MHz bus? I think if the NB was kept VERY close to the processor (say on the underside of the daughter card) it would be possible.</strong><hr></blockquote>



    I dunno, overclocking a motherboard bus by a factor of 2 isn't something that is done very often -- especially by an OEM that must ensure reliability and meet manufacturing standards.
  • Reply 15 of 46
    amorphamorph Posts: 7,112member
    Outsider wrote:



    [quote]<strong>The 133MHz system bus 'limit' on the 7450 is more of a guideline than anything.</strong><hr></blockquote>



    The engineers who wrote the solutions in the FAQ seem to think that the limit is set just below where the part (the MPX bus, not the 7450) becomes unreliable.



    Sure, you can downclock it. But it's not going above 133MHz. And you can't fake 266MHz by clock doubling either, apparently.



    Basically, until the MPX bus either goes away or is significantly revised, the best it can do is 133MHz SDR, according to this FAQ.



    It might be theoretically possible to go to 128-bit MPX - which would not be cheap or easy - and kludge some way to have the DDR fill one half on the uptick and one on the downtick. But somehow I get the feeling that Apple will wait for a new bus first...



    [ 01-22-2002: Message edited by: Amorph ]</p>
  • Reply 16 of 46
    cakecake Posts: 1,010member
    Christ! Regarding the original post - formatting is everything!



    I'll let you other guys distill all of that down for those of us who get a headache and pine for a simple carriage return.
  • Reply 17 of 46
    thttht Posts: 3,249member
    <strong>Originally posted by Amorph:

    Basically, until the MPX bus either goes away or is significantly revised, the best it can do is 133MHz SDR, according to this FAQ.</strong>



    I'm pretty confident they can successively upclock the MPX bus to 167 and 200 MHz in the future. It's all about costs and things get cheaper and doable with better fab tech. If the G5 isn't available in 2002, I can see Apple using a 200 MHz MPX bus with PC2100.



    But yes, Apple is in a waiting game for Moto to implement DDR in the MPX bus and the G5 to come out. Whichever comes first.
  • Reply 18 of 46
    thttht Posts: 3,249member
    <strong>Originally posted by Programmer:

    Having seen some of my code run on both DDR and RamBus equipped machines, I must say that I prefer DDR... at least at the current technology levels. RamBus tends to have very poor latency, much worse than DDR.</strong>



    Granted. But you can't knock the streaming bandwidth of Rambus. It crushes DDR SDRAM. That's single channel as well. Dual-channel it can more than double PC2100. I think Apple's code base would be very suitable to Rambus compared DDR SDRAM.



    <strong>In my experience there isn't much to choose between RamBus and DDR when doing media processing work (i.e. running sequentially through large data sets), but both are much faster than SDRAM. I've seen some algorithms run almost twice as fast.</strong>



    Even dual-channel Rambus solutions v single channel PC2100?



    One of my flights of fancy is a quad short channel Rambus L3 cache for a PPC processor. That's short channel, meaning there's only one RDRAM chip per channel. With only one chip per channel the latency gets to DDR SDRAM levels, gets even smaller since a single chip can clock higher (533+ MHz). Since it's quad channel, the L3 cache can have 6.4 GByte/s of bandwidth. Using a 32 MByte RDRAM chip per channel, that's a whopping 128 MByte L3 cache for a cheap cheap &gt;100$!



    <strong>Add RamBus' politics into the equation and I'd be happy if they curled up and died. Intel seems to be feeling the same way lately.</strong>



    I think it would be terrible for the technology to go away. The corporation can, but hopefully the technology stays.
  • Reply 19 of 46
    FWIW, it *is* possible to link to the original post. The url is:



    <a href="http://e-www.motorola.com/cgi-bin/faq.cgi?kbase=powerpc&search=Search&product=MPC745 0%20%28V%27ger%29" target="_blank">FAQ URL</a>



    [ 01-23-2002: Message edited by: pepp ]</p>
  • Reply 20 of 46
    outsideroutsider Posts: 6,008member
    I think Rambus type memory is the future.



    High speed streaming at small bitwise (serial 8-32bit at 400MHz-1GHZ) versus low speed at high bitwise (parallel 64-128bit at 133-200MHz). The simple reason is that it's easier to design systems and technologies that use small data and address lines and with technology acellerating the way it is, speed(MHz) of the serial transactions goes up regardless.
Sign In or Register to comment.