G4 'tweaks' and 'revs' ... when and how?

Posted:
in Future Apple Hardware edited January 2014
"The G4 has a long life ahead of it," said Joswiak. "There are a number of tweaks and revs that will happen to that processor over a long period of time."





This quote was taken from the Maccentral article this morning. 2 questions (and some follow ups).



1. What constitutes a 'tweak'? Would it be a bus speed increase? DDR Bus? More cache?



2. Does this exclude the G5 in any Apple plans for the year 2002? Can the G4 carry the PowerMac out of 2002 with out sacrificing sales to high end users?
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Comments

  • Reply 1 of 38
    jambojambo Posts: 3,036member
    [quote]Originally posted by Outsider:

    <strong>



    2. Does this exclude the G5 in any Apple plans for the year 2002? Can the G4 carry the PowerMac out of 2002 with out sacrificing sales to high end users?</strong><hr></blockquote>



    Even though he said the G4 has a long life ahead of it he didn't say that it would be in the PowerMac The G4 will carry the iMac/iBook/PowerBook out of 2002. We'll have G5 PowerMacs in a few months.



    J :cool:
  • Reply 1 of 38
    moogsmoogs Posts: 4,296member
    1. Possibly. If the G5 is, in fact, years off - then Apple had better find a way to make the Apollo work on a new mobo setup that includes support for all of the things that are currently missing.



    2. Unless they're pulling our chain, yes. In fact it almost reads to me like you can forget about the G5 - unless Apple's definition of "long period of time" and my definition are wildly different.



    In effect, this news blows goats. Who knows, maybe Steve is trying to bring our expectations down a bit from all the recent articles from Rotherburg and the like. Maybe we will see the G4 in use for "several years to come" - just not in a PM case. Seems an unlikely scenario to me that Apple would lower people's expectations, just to make the G5 a bigger surprise.



    [ 02-11-2002: Message edited by: Moogs ? ]</p>
  • Reply 3 of 38
    g-newsg-news Posts: 1,107member
    We all know what's going to happen if Apple doesn't introduce a new chip within roughly 1.5 years.

    Even if the G4 could close teh GHz gap on its own, it would then face the new Generation gap, and the 32bit gap vs 64bit.

    A new chip is coming our way, and if that doesn't happen until MWTY, that's ok with me.



    G-News
  • Reply 4 of 38
    amorphamorph Posts: 7,112member
    What could they tweak? Any number of things.



    First off, by all accounts that matter (i.e., engineering, not marketing), the 7455 is a home run. The dual GHz appears to be about 30% faster than the dual 800, which tells me that Apple and Mot have done a better job with the 133MHz MaxBus than we give them credit for: If the chips were totally starved, the new processors would hardly have mattered at all.



    So, starting from there: They can upde MaxBus to be double-pumped, they can continue improving the cache architecture, they can tweak, rearrange and add registers and execution units, add support for 2x64 bit integer and float vectors to AltiVec, move it to a smaller process and/or continue adding or refining process improvements like SOI, extend the pipeline, add RapidIO and/or HyperTransport support... and, in short, continue doing what they've been doing with the G4 architecture.



    It's worth hammering home the fact that, as far as I have seen, the only people who are dissappointed in Apple's tower offerings are posters to Mac forums who haven't used them yet. Apple is claiming that it is pleased with sales of the dualie, and I'm not surprised.



    Besides, it's not just CPU performance that determines productivity - in fact, it's not even primary. Hardware and software reliability and ease of use are at least as important.



    [ 02-11-2002: Message edited by: Amorph ]</p>
  • Reply 5 of 38
    [quote]Originally posted by Outsider:

    "The G4 has a long life ahead of it," said Joswiak. "There are a number of tweaks and revs that will happen to that processor over a long period of time."





    This quote was taken from the Maccentral article this morning. 2 questions (and some follow ups).



    1. What constitutes a 'tweak'? Would it be a bus speed increase? DDR Bus? More cache?



    2. Does this exclude the G5 in any Apple plans for the year 2002? Can the G4 carry the PowerMac out of 2002 with out sacrificing sales to high end users?<hr></blockquote>





    1). tweeked to .13 SOI process

    2). It can if there are four of them in the box
  • Reply 6 of 38
    outsideroutsider Posts: 6,008member
    2). It can if there are four of them in the box



    Dude, a quad G4 machine on a 133MHz MPX bus is about as useful as a 5 headed race horse with 3 legs.
  • Reply 7 of 38
    The latest Register article on the subject is interesting -- it claims that Motorola is saying that there are multiple new and subtantially enhanced G4s coming. This includes new bus interfaces and longer pipelines (thus higher clock rates). This is a big enough change to the architecture that I could see it closing the current performance gap. I'm actually a bit surprised that they wouldn't rename such a substantially changed chips to G5, but I'm not going to complain about it.
  • Reply 8 of 38
    [quote]Originally posted by G-News:

    <strong>

    Even if the G4 could close teh GHz gap on its own, it would then face the new Generation gap, and the 32bit gap vs 64bit.

    </strong><hr></blockquote>



    Given that Itanium, Intel's 64-bit chip, is due to debut at 800MHz, I think it would be an interesting reversal...
  • Reply 9 of 38
    leonisleonis Posts: 3,427member
    Check out this article from the register



    <a href="http://www.theregister.co.uk/content/3/24018.html"; target="_blank">http://www.theregister.co.uk/content/3/24018.html</a>;
  • Reply 10 of 38
    [quote]Originally posted by Outsider:

    2). It can if there are four of them in the box



    Dude, a quad G4 machine on a 133MHz MPX bus is about as useful as a 5 headed race horse with 3 legs.<hr></blockquote>





    Actually I was thinking it would use fast paged interleaved memory with RapidIO & HyperTransport - and that would be an 8 legged horse with a head at both ends
  • Reply 11 of 38
    [quote]Originally posted by Aphelion:

    <strong>

    Actually I was thinking it would use fast paged interleaved memory with RapidIO & HyperTransport - and that would be an 8 legged horse with a head at both ends</strong><hr></blockquote>



    RIO and HT? Are you sure you know what you're talking about?



    Bye,

    RazzFazz
  • Reply 12 of 38
    [quote]Originally posted by Leonis:

    <strong>Check out this article from the register



    <a href="http://www.theregister.co.uk/content/3/24018.html"; target="_blank">http://www.theregister.co.uk/content/3/24018.html</a></strong><hr></blockquote>;



    Wow, this is probably the most misinformed (or mis-written, dunno) article I have read in a long time.





    [quote]a crude summary is that a deep pipeline allows the processor to second guess the subsequent instructions, at the cost of clearing the pipeline when it gets the wrong answer.<hr></blockquote>



    So deep pipelines somehow magically do branch prediction? Um, don't think so...





    [quote]RapidIO is a switched fabric interconnect which mirrors the parallel Infiniband initiative: the former is endorsed by the embedded industry, the latter by big iron system vendors, so the two don't really overlap. <hr></blockquote>



    Actually, they are right, the two don't really overlap. But that's not because they are endorsed by different manufacturers, but rather because they target two completely different areas. RapidIO is for chip-to-chip-connections, whereas InfiniBand is for machine-to-machine-connections (see <a href="http://common.ziffdavisinternet.com/util_get_image/0/0,3363,s=1&i=8564,00.jpg"; target="_blank">this diagram</a>, or better yet <a href="http://www.extremetech.com/article/0,3396,s=1005&a=21813,00.asp"; target="_blank">this whole article</a>).





    [quote]In practical terms it will permit the the memory controller to be housed on the die, communicating at full clock speed. So potentially, there's no need for L3 on-die cache.<hr></blockquote>



    RapidIO allows for on-die memory-controllers?

    WTF?

    This is just completely unrelated. RapidIO allows for (surprise, suprise) fast I/O access and chip-to-chip communication, but if your memory controller is already on-die, it won't need RapidIO anymore.



    Also, how exactly is an on-die memory controller going to make L3 cache superfluous unless you also have 500MHz fast memory modules, which aren't even on the horizon?



    Damn, where do those guys get their "inside knowledge" from?



    This sucks.



    Bye,

    RazzFazz



    [ 02-12-2002: Message edited by: RazzFazz ]</p>
  • Reply 13 of 38
    stoostoo Posts: 1,490member
    [quote]an 8 legged horse with a head at both ends

    <hr></blockquote>



    Which way does that run?



    I think that the G5 disappointment partly comes from G5's rumoured performance gains and its non-appearance: too much over optimistic hype.



    [quote]So potentially, there's no need for L3 on-die cache.<hr></blockquote>



    The G4's L3 cache is what keeps it from bandwidth starvation (without it dual CPUs would be much less practical). Hopefully DDR main memory Macs will still come with L3 cache.
  • Reply 14 of 38
    [quote]Originally posted by Stoo:

    <strong>

    The G4's L3 cache is what keeps it from bandwidth starvation (without it dual CPUs would be much less practical). Hopefully DDR main memory Macs will still come with L3 cache.</strong><hr></blockquote>



    Not really, it's way to small to really help with bandwidth-intensive apps (the complete 2MB of L3 would be emptied in half a millisecond).

    It helps with latency, not bandwidth. But for exactly this reason, L3 is still desirable even with DDR memory. DDR266 may offer up to twice the bandwidth of PC133, but it still only has the same latency.



    Bye,

    RazzFazz



    [ 02-12-2002: Message edited by: RazzFazz ]</p>
  • Reply 15 of 38
    The fast L3 caches in the current machines are very expensive. In a machine with a 1.5GHz processor, faster bus, DDR memory, and a 512K on-chip L2, the use of an L3 might not be worth the money or the large number of pins that it uses on the chip (not to mention all the circuitry for the tags and cache controller). As a result it wouldn't surprise me at all to see it disappear.
  • Reply 16 of 38
    [quote]Originally posted by Programmer:

    <strong>In a machine with a 1.5GHz processor, faster bus, DDR memory, and a 512K on-chip L2, the use of an L3 might not be worth the money or the large number of pins that it uses on the chip (not to mention all the circuitry for the tags and cache controller). As a result it wouldn't surprise me at all to see it disappear.</strong><hr></blockquote>



    Well, in fact, I was quite surprised Apple actually introduced L3 at all in the first place. Surprised in a positive way, that is. Doesn't happen too often, but obviously does happen every now and then.



    I'd hate to see it go away, but it wouldn't be the end of the world either, I guess...



    Bye,

    RazzFazz
  • Reply 17 of 38
    [quote]Originally posted by RazzFazz:

    <strong>



    RIO and HT? Are you sure you know what you're talking about?



    Bye,

    RazzFazz</strong><hr></blockquote>



    Here's what I was referring to:



    Serial RapidIO provides al solution that overcomes the limitations of parallel buses for the control path. RapidIO provides a link bandwidth that is comparable to PCI, with the benefit of scaleability beyond PCI through the use of a switched fabric architecture. Also, because the bus arbitration problem is eliminated, a high degree of concurrent peer-to-peer interconnection is possible. Serial RapidIO only consumes four pins on a backplane, providing a very efficient, reliable interconnect.



    The RapidIO protocol is divided into three layers - the logical layer, the transport layer, and the physical layer The logical layer contains the logical abstraction for communication. This includes three types of I/Os - memory-mapped, global shared memory, and message passing.



    Of the three I/Os, the memory-mapped I/O is probably the most significant in the serial RapidIO structure. The term memory-mapped I/O is used to describe a scheme where hardware registers respond to addresses in memory space. These registers provide windows in memory space to the I/O functions such as an input FIFO. The transport layer defines how data packets are transmitted between end-points through the fabric. Latency is important in these systems. As a result, routing is simplified in RapidIO switches.





    Hypertransport focuses on the bottlenecks created by the interface between processors in most networking designs. Companies like Intel, AMD, and Motorola are working on technologies like HyperTransport, RapidIO, Arapahoe (3GIO), and the other new processor interconnects.



    HyperTransport technology is a high speed, high performance point-to-point link for interconnecting integrated circuits on a motherboard. It can be significantly faster than a PCI bus. It was previously codenamed Lightning Data Transport, or LDT. HyperTransport was invented by AMD and perfected with the help of several partners throughout the industry. The technology targets networking, telecommunications, computers and embedded systems and any application where high speed, low latency and scalability are necessary.



    HyperTransport is designed to provide more bandwidth than current technologies, using low-latency responses, low pin counts, compatiblity with legacy PC buses, be extensible to new SNA (Systems Network Architecture) buses, be transparent to operating systems and offer little impact on peripheral drivers. Its electrical design is designed to improve reliability and reduce board design complexity.



    If designers want to choose between the two, they could easily find a situation where one chip has a HyperTransport interface, while the others have a RapidIO interconnect. That means another piece of silicon, probably an FPGA or PLD, is needed to interface the processors together.



    My point (to Outsider) was that a Quad (or greater) system would not need to be hobbled by a 133 MHz bus as seen in current systems. I made the assumption that Apple wouldn't just duct tape three more processors somewhere in the case. This is future hardware after all.
  • Reply 18 of 38
    sc_marktsc_markt Posts: 1,393member
    If the G5 is released at MWNY '02, then I could see these new G4's being used for the iMacs and Powerbooks.
  • Reply 19 of 38
    Listen, the fact that the G4 has a long life ahead of it means NOTHING about Powermac G5s.



    The G4 is going to be in laptops and iMacs for many years, obviously...this is not news.



    The current situation is analogous to back when the Powermacs and iMac shared the G3. The G3 had a long life, and is in fact still going strong, but that didn't mean that it was destined to live out its years in the Powermac. Same with the G4.



    G5 MWNY, or MWSF at the latest.
  • Reply 20 of 38
    [quote]Originally posted by Aphelion:

    <strong>

    (long text about RIO and HT)

    </strong><hr></blockquote>



    Well, my point was that it would be pretty useless for Apple to include both RapidIO and HyperTransport in their systems, as this would be kinda redundant.



    Bye,

    RazzFazz
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