<strong>hmm... a well designed/simple architecture is not a substitute for technological advancement. The things I describe - that motorola is not acting on - ARE optimizations, and DO make things execute in shorter time.
</strong><hr></blockquote>
Well, from what I understand, SMT lends itself very well to "narrow and deep" architectures like the P4, whereas a "shallow and broad" architecture like the one of the G4 would hardly benefit from it, if at all.
So just because SMT is indeed an optimization for the P4 doesn't mean it should also be included in the G4 right away.
"So just because SMT is indeed an optimization for the P4 doesn't mean it should also be included in the G4 right away"
the point is not that it belongs in the G4 architecture... just that it could/should belong in a future implementation of the PPC ISA. The G4 is only one implementation of that ISA...
EDIT: spelling...
[ 02-28-2002: Message edited by: grad student ]</p>
Considering that the 7450 topped out at what, 866mhz, and the 7455 is the same processor on a SOI process, and SOI yeilds a maximum of 30% increase in clockspeed, i think we can rule out 2Ghz G4s in this lifetime.
"Motorola is currently running embedded microprocessor cores on this advanced 0.13 micron process. "
Also note the following quote from their press release.
"This HiP7 technology is the latest development in Motorola's continuous scaling of CMOS process technology. It is commonly referred to as 0.13 micron but contains minimum features of 0.07 micron"
I don't know how long it takes to migrate an architecture to a new process, but 11 months seems like a long time. I really was expecting HiP7 in January, BIG MISTAKE.
I had $1800 ready to spend for a low end tower in Jan. Between the lack of a significatnt processor improvement and motherboard stagnation, I haven't bought. Instead, for ~$300 I bought a 7500 and G4 upgrade card to at least tide me over until Apple/Motorola delivers. Then my childrem will get a very good computer for whatever.
Dear Apple the money is here, just waiting and waiting and waiting.
One other thing: The roadmap also says the G4 is "migrating to SOI," which they've just done with these new 7455 chips. But it says nothing about the G4 migrating to a smaller process. So will they just start their smaller process with the G5 and never do a smaller G4?
"How come motorola has not put a .13micron process into their processors?"
They're in the process of doing that. It's called the HiP7 process. Motorola is already manufacturing some chips on this process right now. It takes time before it's entire product line can be migrated to this process. There is also a learning experience involved. This is why they sort of experiment with one of their product lines first.
"I know for a fact that put The MPC7455 processor to .13micron process will push it alot higher than 1.4GHz. "
That sounds reasonable.
"If G5 is coming out which it will not until they change to .13micron process."
Again, Motorola is already manufacturing some chips at .13u. The G5 will likely debut on the .13u process, but this is completely independent of what they are doing with the G4 chips. We may see .13u G4s either before or after the G5 introduction.
"Yes, the MPC7455 processor at .18micron process can reach a maxium speed of about 1.8Ghz and maybe alittle higher according to motorola. "
Where did Motorola state this? That seems a bit far fetched to me. I'm sure it can go higher than 1GHZ, but remember, Apple needs sufficient yields in order to have dual processor machines at the high end. We've already seen the 1GHZ machines overclocked to 1.2GHZ. I don't doubt some can go a bit further. I wouldn't expect more than 1.3 - 1.4GHZ out of the .13u G4s, even if they are capable of a bit more. I'm sure Apple will play things a bit on the conservative side in order to avoid the embarassment they went through with the original 500mhz G4s.
"The G5 will need a .13micron process to reach a speed over 3Ghz. You have to remember the G5 will come with a bus improvment and a higher speed memory. Common sense. "
Not true. "Improved bus" and "higher speed memory" have nothing to do with a chip's maximum clock speed. The G5 will likely scale a bit higher than the G4 on the same manufacturing process, but it will be due to architectural changes such as a longer instruction pipeline (thereby reducing the timing of each individual step). 3 GHZ is well beyond any prediction I've seen from Motorola regarding the G5 on it's initial production process. Without knowing more about the G5, it's difficult to predict how it will scale. I'd say 2GH on .13u is more reasonable.
One thing to note is that as the manufacturing process changes, you typically get a few extras, such as increased L2 cache. Likewise, a 1.4 GHZ (.13u) G4 will probably be a pretty good performer.
This may clear up some of the confusion over the process size. The poster @ Arstechnica, BadAndy, is apparently extremely knowledgable concerning microprocessor architecture and design.
yes, there was a while where Moto's flacks were calling what really was a 0.18 micron process 0.13 ... but that's over.
Moto's HIP-7 process is a good 0.13 micron process with fancy stuff: SOI, fancy dialectrics, and of course Cu.
See chip-architect.com for discussion of the HIP-7 process, and shared development with AMD (the article is rather slanted toward hyping AMD, but it doesn't matter... good info there)
And yes, Moto has been "producing" parts on HIP-7 for some time, but this is prototype production and testing stuff. I don't know of ANY routine-production HIP-7 hardware ... but the MPC8540 may be the first.
There is one very interesting thought... the MPC7455 and '45 may be coming through the HIP-7 process lines, with 0.18 micron lithography.
I've had this thought for some time, and wished I knew a way to check it. In principle it shouldn't be too hard to find out.
If true this would make very good sense: get some production to help amortize the fab (oh god are the capital carrying costs a burden on a fab which is not yet in production), while you fiddle. The 0.18 micron lithography wouldn't require tricky phase-compensation masks, and would stress other aspects of the system to a lesser degree also.
My impression very strongly is that the '55 is a interim part in many regards; built mostly for Apple and not expected to have a lengthy product cycle. The '45 (really the same part) may last longer.
Both should be obsoleted when Motorola gets full 0.13 micron production. "Obsolete" parts last a long time (at low prices) in the embedded marketplace, but they disappear very quickly from desktop production.<hr></blockquote>
So is their .20 or .18 = .15? I'm starting to think their roadmap is just meaningless.</strong>
When Motorola shipped the MPC7400, the first G4, they said it was fabbed on a 0.15u process (HiP 5 with Cu interconnects). The 0.15u number was a Leff as far as I can tell. From the die size area, the MPC7400 was fabbed on a 0.22u micron drawn process.
<strong>And then is the initial G5 going to be .15 rather than .13? They call it .13, but is that really what it means?</strong>
The next process is HiP 7 which will be a 0.13u drawn process. HiP 6 was 0.18u.
<strong>One other thing: The roadmap also says the G4 is "migrating to SOI," which they've just done with these new 7455 chips. But it says nothing about the G4 migrating to a smaller process. So will they just start their smaller process with the G5 and never do a smaller G4?
</strong>
The G4 fabbed on a 0.13 micron will be a very nice embedded processor, not to mention a laptop and desktop processor either. Motorola would be foolish not too.
It looks like .15 will be skipped and they'll be going right to .13, then.
BTW, the G3 will be moving to .13 with the IBM 750fx (Sahra) in the very near future, if it hasn't already. Hopefully we'll see that in the iBook right away, with some longer battery life and higher Mhz.
[quote]Mine are probably running 70 C or hotter under full load.<hr></blockquote>
Ermm that sounds a little hot dude. My G4 runs at ~35C full load. An Athlon should never get over ~60C or it can be dangerous...not sure why G4s are special. <img src="confused.gif" border="0">
Not trying to pick on anyone, but for the sake of keeping these kinds of threads useful, how about from now on, we leave the f*cking Motorola "Roadmap" OUT OF THE EQUATION?
Seems most people know said document has aboslutely no credibility / bearing on where MOT is actually headed with its semiconductor products for the desktop - yet some people still insist on using it as evidence. For what I have no idea because the document is not binding, is not specific and is not even accurate in its terminology.
KILL the roadmap talk - please... there's enough static in this forum to begin with. Adding useless variables like Motorola's vaunted "Roadmap" to the equation only makes for more noise and less understanding.
<strong>Not trying to pick on anyone, but for the sake of keeping these kinds of threads useful, how about from now on, we leave the f*cking Motorola "Roadmap" OUT OF THE EQUATION?</strong><hr></blockquote>Uh, OK.
<strong>"So just because SMT is indeed an optimization for the P4 doesn't mean it should also be included in the G4 right away"
the point is not that it belongs in the G4 architecture... just that it could/should belong in a future implementation of the PPC ISA. The G4 is only one implementation of that ISA...
EDIT: spelling...
[ 02-28-2002: Message edited by: grad student ]</strong><hr></blockquote>
"grad student"?
oh right, like in Good Will Hunting!!!
<...something about giant simian testicles...>
Well, guess I shouldn't have said "narrow", but it's certainly true for "deep". As Mr. DeMone says, the situations where SMT is useful are caused by "memory stalls, branch misprediction, instruction dependencies etc inherent in single thread execution", which have much more impact (and as such present much more opportunity to benefit from SMT) in deeply pipelined architectures, whereas architectures with shorter pipelines can keep their execution units occupied much better (and SMT only works if you have EUs that are not in use in the first place).
Also, he claims that on the EV8, the speedup would have been "100% or more" - I wonder how this would be possible, given that even with SMT, there's still just a single pipeline that can only fetch and retire a given number of instructions per clock. Is he assuming the EV8 couldn't possibly keep half of its EUs busy without SMT?
Bye,
RazzFazz
BTW: Who is that Paul DeMone? Anyone I should know?
Comments
<strong>hmm... a well designed/simple architecture is not a substitute for technological advancement. The things I describe - that motorola is not acting on - ARE optimizations, and DO make things execute in shorter time.
</strong><hr></blockquote>
Well, from what I understand, SMT lends itself very well to "narrow and deep" architectures like the P4, whereas a "shallow and broad" architecture like the one of the G4 would hardly benefit from it, if at all.
So just because SMT is indeed an optimization for the P4 doesn't mean it should also be included in the G4 right away.
Bye,
RazzFazz
<strong>Maybe a little off topic, but what are the fundemental differences from Hyperstransport, and RapidIO?</strong><hr></blockquote>
For a good explanation of both of them, and a limited comparison, look <a href="http://www.extremetech.com/article/0,3396,s=1005&a=21813,00.asp"; target="_blank">here</a>.
Bye,
RazzFazz
the point is not that it belongs in the G4 architecture... just that it could/should belong in a future implementation of the PPC ISA. The G4 is only one implementation of that ISA...
EDIT: spelling...
[ 02-28-2002: Message edited by: grad student ]</p>
If Motorola stays in the financial tank, you may see process generations contiunue to fall behind.
<a href="http://www.corporate-ir.net/ireye/ir_site.zhtml?ticker=mot&script=411&layout=-6&item_id=164832"; target="_blank">http://www.corporate-ir.net/ireye/ir_site.zhtml?ticker=mot&script=411&layout=-6&item_id=164832</a>;
"Motorola is currently running embedded microprocessor cores on this advanced 0.13 micron process. "
Also note the following quote from their press release.
"This HiP7 technology is the latest development in Motorola's continuous scaling of CMOS process technology. It is commonly referred to as 0.13 micron but contains minimum features of 0.07 micron"
I don't know how long it takes to migrate an architecture to a new process, but 11 months seems like a long time. I really was expecting HiP7 in January, BIG MISTAKE.
I had $1800 ready to spend for a low end tower in Jan. Between the lack of a significatnt processor improvement and motherboard stagnation, I haven't bought. Instead, for ~$300 I bought a 7500 and G4 upgrade card to at least tide me over until Apple/Motorola delivers. Then my childrem will get a very good computer for whatever.
Dear Apple the money is here, just waiting and waiting and waiting.
So is their .20 or .18 = .15? I'm starting to think their roadmap is just meaningless.
And then is the initial G5 going to be .15 rather than .13? They call it .13, but is that really what it means?
Other info available on their <a href="http://e-www.motorola.com/webapp/sps/site/taxonomy.jsp?nodeId=03M943030450467M98653"; target="_blank"> G4 processor specs page</a>.
One other thing: The roadmap also says the G4 is "migrating to SOI," which they've just done with these new 7455 chips. But it says nothing about the G4 migrating to a smaller process. So will they just start their smaller process with the G5 and never do a smaller G4?
again:
"How come motorola has not put a .13micron process into their processors?"
They're in the process of doing that. It's called the HiP7 process. Motorola is already manufacturing some chips on this process right now. It takes time before it's entire product line can be migrated to this process. There is also a learning experience involved. This is why they sort of experiment with one of their product lines first.
"I know for a fact that put The MPC7455 processor to .13micron process will push it alot higher than 1.4GHz. "
That sounds reasonable.
"If G5 is coming out which it will not until they change to .13micron process."
Again, Motorola is already manufacturing some chips at .13u. The G5 will likely debut on the .13u process, but this is completely independent of what they are doing with the G4 chips. We may see .13u G4s either before or after the G5 introduction.
"Yes, the MPC7455 processor at .18micron process can reach a maxium speed of about 1.8Ghz and maybe alittle higher according to motorola. "
Where did Motorola state this? That seems a bit far fetched to me. I'm sure it can go higher than 1GHZ, but remember, Apple needs sufficient yields in order to have dual processor machines at the high end. We've already seen the 1GHZ machines overclocked to 1.2GHZ. I don't doubt some can go a bit further. I wouldn't expect more than 1.3 - 1.4GHZ out of the .13u G4s, even if they are capable of a bit more. I'm sure Apple will play things a bit on the conservative side in order to avoid the embarassment they went through with the original 500mhz G4s.
"The G5 will need a .13micron process to reach a speed over 3Ghz. You have to remember the G5 will come with a bus improvment and a higher speed memory. Common sense. "
Not true. "Improved bus" and "higher speed memory" have nothing to do with a chip's maximum clock speed. The G5 will likely scale a bit higher than the G4 on the same manufacturing process, but it will be due to architectural changes such as a longer instruction pipeline (thereby reducing the timing of each individual step). 3 GHZ is well beyond any prediction I've seen from Motorola regarding the G5 on it's initial production process. Without knowing more about the G5, it's difficult to predict how it will scale. I'd say 2GH on .13u is more reasonable.
One thing to note is that as the manufacturing process changes, you typically get a few extras, such as increased L2 cache. Likewise, a 1.4 GHZ (.13u) G4 will probably be a pretty good performer.
Steve
[quote]BadAndy
Smack-Fu Master, in training
Tribus: Albany, NY, USA
Registered: May 07, 2001
Posts: 161
\t
posted March 01 2002, 12:23 PM Â*
------------------------------------------------------------------------
0.13 micron process... etc
Forgot to address that.
yes, there was a while where Moto's flacks were calling what really was a 0.18 micron process 0.13 ... but that's over.
Moto's HIP-7 process is a good 0.13 micron process with fancy stuff: SOI, fancy dialectrics, and of course Cu.
See chip-architect.com for discussion of the HIP-7 process, and shared development with AMD (the article is rather slanted toward hyping AMD, but it doesn't matter... good info there)
And yes, Moto has been "producing" parts on HIP-7 for some time, but this is prototype production and testing stuff. I don't know of ANY routine-production HIP-7 hardware ... but the MPC8540 may be the first.
There is one very interesting thought... the MPC7455 and '45 may be coming through the HIP-7 process lines, with 0.18 micron lithography.
I've had this thought for some time, and wished I knew a way to check it. In principle it shouldn't be too hard to find out.
If true this would make very good sense: get some production to help amortize the fab (oh god are the capital carrying costs a burden on a fab which is not yet in production), while you fiddle. The 0.18 micron lithography wouldn't require tricky phase-compensation masks, and would stress other aspects of the system to a lesser degree also.
My impression very strongly is that the '55 is a interim part in many regards; built mostly for Apple and not expected to have a lengthy product cycle. The '45 (really the same part) may last longer.
Both should be obsoleted when Motorola gets full 0.13 micron production. "Obsolete" parts last a long time (at low prices) in the embedded marketplace, but they disappear very quickly from desktop production.<hr></blockquote>
<a href="http://arstechnica.infopop.net/OpenTopic/page?a=tpc&s=50009562&f=8300945231&m=1770949283&r= 5920949983#5920949983" target="_blank">Here's the link</a>
<a href="http://e-www.motorola.com/webapp/sps/site/overview.jsp?nodeId=03M943030450467M983989030230"; target="_blank">On their roadmap,</a> they say that the G4 initial product was .15, when actually it's never reached .15. It's still at .18. And the first G4 to go to .18 was the 7410 - the initial G4 product, at least in a Mac, was .20.
So is their .20 or .18 = .15? I'm starting to think their roadmap is just meaningless.</strong>
When Motorola shipped the MPC7400, the first G4, they said it was fabbed on a 0.15u process (HiP 5 with Cu interconnects). The 0.15u number was a Leff as far as I can tell. From the die size area, the MPC7400 was fabbed on a 0.22u micron drawn process.
<strong>And then is the initial G5 going to be .15 rather than .13? They call it .13, but is that really what it means?</strong>
The next process is HiP 7 which will be a 0.13u drawn process. HiP 6 was 0.18u.
<strong>One other thing: The roadmap also says the G4 is "migrating to SOI," which they've just done with these new 7455 chips. But it says nothing about the G4 migrating to a smaller process. So will they just start their smaller process with the G5 and never do a smaller G4?
</strong>
The G4 fabbed on a 0.13 micron will be a very nice embedded processor, not to mention a laptop and desktop processor either. Motorola would be foolish not too.
It looks like .15 will be skipped and they'll be going right to .13, then.
BTW, the G3 will be moving to .13 with the IBM 750fx (Sahra) in the very near future, if it hasn't already. Hopefully we'll see that in the iBook right away, with some longer battery life and higher Mhz.
[quote]Mine are probably running 70 C or hotter under full load.<hr></blockquote>
Ermm that sounds a little hot dude. My G4 runs at ~35C full load. An Athlon should never get over ~60C or it can be dangerous...not sure why G4s are special. <img src="confused.gif" border="0">
<strong>
Well, from what I understand, SMT lends itself very well to "narrow and deep" architectures like the P4
</strong><hr></blockquote>
Um No.
Not according to Paul DeMone <a href="http://arstechnica.infopop.net/OpenTopic/page?a=tpc&s=50009562&f=174096756&m=9250968162&r=9 990941262#9990941262" target="_blank">link</a>
Seems most people know said document has aboslutely no credibility / bearing on where MOT is actually headed with its semiconductor products for the desktop - yet some people still insist on using it as evidence. For what I have no idea because the document is not binding, is not specific and is not even accurate in its terminology.
KILL the roadmap talk - please... there's enough static in this forum to begin with. Adding useless variables like Motorola's vaunted "Roadmap" to the equation only makes for more noise and less understanding.
<strong>Not trying to pick on anyone, but for the sake of keeping these kinds of threads useful, how about from now on, we leave the f*cking Motorola "Roadmap" OUT OF THE EQUATION?</strong><hr></blockquote>Uh, OK.
<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
[ 03-02-2002: Message edited by: BRussell ]</p>
<strong>"So just because SMT is indeed an optimization for the P4 doesn't mean it should also be included in the G4 right away"
the point is not that it belongs in the G4 architecture... just that it could/should belong in a future implementation of the PPC ISA. The G4 is only one implementation of that ISA...
EDIT: spelling...
[ 02-28-2002: Message edited by: grad student ]</strong><hr></blockquote>
"grad student"?
oh right, like in Good Will Hunting!!!
<...something about giant simian testicles...>
<strong>
Um No.
Not according to Paul DeMone <a href="http://arstechnica.infopop.net/OpenTopic/page?a=tpc&s=50009562&f=174096756&m=9250968162&r=9 990941262#9990941262" target="_blank">link</a></strong><hr></blockquote>
Well, guess I shouldn't have said "narrow", but it's certainly true for "deep". As Mr. DeMone says, the situations where SMT is useful are caused by "memory stalls, branch misprediction, instruction dependencies etc inherent in single thread execution", which have much more impact (and as such present much more opportunity to benefit from SMT) in deeply pipelined architectures, whereas architectures with shorter pipelines can keep their execution units occupied much better (and SMT only works if you have EUs that are not in use in the first place).
Also, he claims that on the EV8, the speedup would have been "100% or more" - I wonder how this would be possible, given that even with SMT, there's still just a single pipeline that can only fetch and retire a given number of instructions per clock. Is he assuming the EV8 couldn't possibly keep half of its EUs busy without SMT?
Bye,
RazzFazz
BTW: Who is that Paul DeMone? Anyone I should know?