<strong>The G4 would need major modifications to use a DDR bus. The easiest way is for them to design a SDR bus that operates at a higher frequency. 200MHz would give you 1.6GB per sec and then using PC2100 RAM would make more sense.</strong><hr></blockquote>
Bad andy over at Ars Technica has been posting some really amazing AltiVec stuff, and his constant factor is that it's incredibly membory bound and increasing MHz will likely do very little for many operations right now.
If a 2GHz G4 with SDRAM is released, it won't be worth buying tomorrow.
DDR is very needed, but would require changes to core components which must be nasty to do.
DDR is very needed, but would require changes to core components which must be nasty to do.</strong>
I wouldn't think so. I think it's more a case of Motorola being lazy or simply not wanting to. They don't even support the MPX bus in their own chipsets, let alone a DDR bus. Motorola was willing to implement a DDR backside bus, so one wonders why they didn't try with the processor bus at the same time...
DDR is very needed, but would require changes to core components which must be nasty to do.</strong>
I wouldn't think so. I think it's more a case of Motorola being lazy or simply not wanting to. They don't even support the MPX bus in their own chipsets, let alone a DDR bus. Motorola was willing to implement a DDR backside bus, so one wonders why they didn't try with the processor bus at the same time...
The only thing I can think of is that, in the embedded markets, the off-chip cache often is the system RAM, and there is sufficient demand in that market for DDR SDRAM L3 cache. Meanwhile, for system communications, the MaxBus/60x bus architecture was considered adequate.
That's a pure guess, though.
Aside from the obvious problems (shorter traces, interference problems, higher sensitivity, etc.) what would make a clock-doubled bus difficult on the G4? Anyone? It seems that the MaxBus does a lot of delicate work in order to use its bandwidth efficiently and reduce latency; does that make it difficult (or expensive, or both) to double the clock and preserve backward compatibility? Is compatibility between DDR and SDR implementations ever an issue?
The only thing I can think of is that, in the embedded markets, the off-chip cache often is the system RAM, and there is sufficient demand in that market for DDR SDRAM L3 cache. Meanwhile, for system communications, the MaxBus/60x bus architecture was considered adequate.</strong>
Perhaps. If true, more reason for Apple to take PPC processor design in-house.
<strong>Aside from the obvious problems (shorter traces, interference problems, higher sensitivity, etc.) what would make a clock-doubled bus difficult on the G4? Anyone?</strong>
I can't think of a thing.
<strong>It seems that the MaxBus does a lot of delicate work in order to use its bandwidth efficiently and reduce latency; does that make it difficult (or expensive, or both) to double the clock and preserve backward compatibility? </strong>
The clock isn't doubled. All PC2100 RAM operate at 133 MHz clock rate just like PC133 does. It's double data rate, sort of like AGP 2x. Data can be sent on the rising and falling edges of the sinusoidal clock signal, and therefore double its theoretical data rate.
<strong>Is compatibility between DDR and SDR implementations ever an issue?</strong>
It shouldn't matter. Apple uses the current UniNorth chipset for iBooks, iMacs. This should be zero development. The new chipset would be used for Power Macs and Powerbooks. As time moves by, the DDR chipset moves down to the consumer hardware.
<strong>It shouldn't matter. Apple uses the current UniNorth chipset for iBooks, iMacs.</strong><hr></blockquote>
Nope, they don't.
Currently, the UniNorth and KeyLargo combo is used in PowerMacs and -Books, whereas the integrated Pangea controller is used in iMacs and -Books. Block diagrams can be found in the docs linked to from <a href="http://developer.apple.com/techpubs/hardware/hardware.html"; target="_blank">this page</a>.
EDIT: Or did you mean they should use UN and KL rather than Pangea in the iMac/iBook in the future? If so, what would be the point?
The only thing I can think of is that, in the embedded markets, the off-chip cache often is the system RAM, and there is sufficient demand in that market for DDR SDRAM L3 cache. Meanwhile, for system communications, the MaxBus/60x bus architecture was considered adequate.</strong>
Perhaps. If true, more reason for Apple to take PPC processor design in-house.
<strong>Aside from the obvious problems (shorter traces, interference problems, higher sensitivity, etc.) what would make a clock-doubled bus difficult on the G4? Anyone?</strong>
I can't think of a thing.
[quote]
Posted by Amorph:
It seems that the MaxBus does a lot of delicate work in order to use its bandwidth efficiently and reduce latency; does that make it difficult (or expensive, or both) to double the clock and preserve backward compatibility?
<strong>The clock isn't doubled. All PC2100 RAM operate at 133 MHz clock rate just like PC133 does. It's double data rate, sort of like AGP 2x. Data can be sent on the rising and falling edges of the sinusoidal clock signal, and therefore double its theoretical data rate.</strong><hr></blockquote>
Oof. I knew that. I might be mistaken, but I thought that was what "clock-doubling" was shorthand for?
What I meant was, would there be a large number of problems inherent in taking an efficient SDR bus architecture to DDR? Has anyone ever tried, or is it more common to just design a new bus around DDR?
What I meant was, would there be a large number of problems inherent in taking an efficient SDR bus architecture to DDR? Has anyone ever tried, or is it more common to just design a new bus around DDR?</strong><hr></blockquote>
Well, at least the Athlon's DDR and the P4's QDR bus were completely designs AFAIU.
Dunno for the bus between northbridge and RAM modules, though.
"10% to 20% gain doesn't seem worth it. Apple is probably on the right track with DDR "<hr></blockquote>
In the summary of the Tom's Hardware article you linked to, this is what the author had to say," [quote]The introduction of DDR SDRAM is indeed an impressive thing. Performance gains of over 10% are worth a lot of respect. We have never seen anything like that ever before with any other new memory type.<hr></blockquote>
just the Tom's Hardware author's 2 cents</strong><hr></blockquote>
In terms of memory speed, it is a big thing. In terms of overall computer speed I think a lot of people assume that double data rate (DDR) means the computer will be twice as fast, au contraire, most users woudn't see any difference... so why should apple add this feature to the legacy G4 if new processors are coming out. In fact, I think the fact that Apple does not try to get Moto to make DDR possible means that indeed a new chip (and new motherboard) is on the horizon (duh). If it were me, I would make a new motherboard that will work with the G4 and what ever the new chip will be called.
Wasn't it around the 1Ghz mark when Intel/AMD started introducing DDR? There wasn't much of a need when the fastest processor was 500Mhz, but now that we're at 1Ghz, now would the proper time...
I'm no expert, but it's probably only now that the G4 is really starting to feel the effects of the slow memory bus, not a year ago.
[ 03-31-2002: Message edited by: Bozo the Clown ]</p>
Actually, AltiVec has a voracious appetite for bandwidth -- even a 400 MHz G4 is memory bound on some algorithms. On these kinds of algorithms DDR can double a machine's speed. People often seem to think that machine is either twice as fast or it isn't -- this is a fallacy. Some machines are better at some tasks and worse at others. This is one reason why synthetic benchmarks are of dubious value, and also why Apple can usually find particular tasks for its "bake-off" demos where the G4 clobbers the competition.
Comments
<strong>10% to 20% gain doesn't seem worth it. Apple is probably on the right track with DDR cache.
<a href="http://www6.tomshardware.com/mainboard/00q4/001030/athlon-15.html"; target="_blank">DDR speed</a></strong><hr></blockquote>
<img src="graemlins/oyvey.gif" border="0" alt="[No]" /> <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
wow, so when Apple move to Dual 1.4 Ghz G4 ( If that ever happens), it still wouldnt be worth to move to a more modern memory sub-system?
You are paying 3K for a dual 1 Ghz G4, and IMO it should support some modern memory standard.
[ 03-29-2002: Message edited by: blabla ]</p>
<strong>The G4 would need major modifications to use a DDR bus. The easiest way is for them to design a SDR bus that operates at a higher frequency. 200MHz would give you 1.6GB per sec and then using PC2100 RAM would make more sense.</strong><hr></blockquote>
Yes, major modifications. It's called the G5.
<strong>
<img src="graemlins/oyvey.gif" border="0" alt="[No]" /> <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
wow, so when Apple move to Dual 1.4 Ghz G4 ( If that ever happens), it still wouldnt be worth to move to a more modern memory sub-system?
You are paying 3K for a dual 1 Ghz G4, and IMO it should support some modern memory standard.
[ 03-29-2002: Message edited by: blabla ]</strong><hr></blockquote>
OK. Let's say the up the processors to 1.2Ghz and add DDR. I wouldn't complain about a 30-40% performance increase....
If a 2GHz G4 with SDRAM is released, it won't be worth buying tomorrow.
DDR is very needed, but would require changes to core components which must be nasty to do.
DDR is very needed, but would require changes to core components which must be nasty to do.</strong>
I wouldn't think so. I think it's more a case of Motorola being lazy or simply not wanting to. They don't even support the MPX bus in their own chipsets, let alone a DDR bus. Motorola was willing to implement a DDR backside bus, so one wonders why they didn't try with the processor bus at the same time...
[ 03-29-2002: Message edited by: THT ]</p>
<strong>[qb]Originally posted by KD5MDK:
DDR is very needed, but would require changes to core components which must be nasty to do.</strong>
I wouldn't think so. I think it's more a case of Motorola being lazy or simply not wanting to. They don't even support the MPX bus in their own chipsets, let alone a DDR bus. Motorola was willing to implement a DDR backside bus, so one wonders why they didn't try with the processor bus at the same time...
[ 03-29-2002: Message edited by: THT ][/QB]<hr></blockquote>
The only thing I can think of is that, in the embedded markets, the off-chip cache often is the system RAM, and there is sufficient demand in that market for DDR SDRAM L3 cache. Meanwhile, for system communications, the MaxBus/60x bus architecture was considered adequate.
That's a pure guess, though.
Aside from the obvious problems (shorter traces, interference problems, higher sensitivity, etc.) what would make a clock-doubled bus difficult on the G4? Anyone? It seems that the MaxBus does a lot of delicate work in order to use its bandwidth efficiently and reduce latency; does that make it difficult (or expensive, or both) to double the clock and preserve backward compatibility? Is compatibility between DDR and SDR implementations ever an issue?
[ 03-29-2002: Message edited by: Amorph ]</p>
The only thing I can think of is that, in the embedded markets, the off-chip cache often is the system RAM, and there is sufficient demand in that market for DDR SDRAM L3 cache. Meanwhile, for system communications, the MaxBus/60x bus architecture was considered adequate.</strong>
Perhaps. If true, more reason for Apple to take PPC processor design in-house.
<strong>Aside from the obvious problems (shorter traces, interference problems, higher sensitivity, etc.) what would make a clock-doubled bus difficult on the G4? Anyone?</strong>
I can't think of a thing.
<strong>It seems that the MaxBus does a lot of delicate work in order to use its bandwidth efficiently and reduce latency; does that make it difficult (or expensive, or both) to double the clock and preserve backward compatibility? </strong>
The clock isn't doubled. All PC2100 RAM operate at 133 MHz clock rate just like PC133 does. It's double data rate, sort of like AGP 2x. Data can be sent on the rising and falling edges of the sinusoidal clock signal, and therefore double its theoretical data rate.
<strong>Is compatibility between DDR and SDR implementations ever an issue?</strong>
It shouldn't matter. Apple uses the current UniNorth chipset for iBooks, iMacs. This should be zero development. The new chipset would be used for Power Macs and Powerbooks. As time moves by, the DDR chipset moves down to the consumer hardware.
[ 03-29-2002: Message edited by: THT ]</p>
<strong>It shouldn't matter. Apple uses the current UniNorth chipset for iBooks, iMacs.</strong><hr></blockquote>
Nope, they don't.
Currently, the UniNorth and KeyLargo combo is used in PowerMacs and -Books, whereas the integrated Pangea controller is used in iMacs and -Books. Block diagrams can be found in the docs linked to from <a href="http://developer.apple.com/techpubs/hardware/hardware.html"; target="_blank">this page</a>.
EDIT: Or did you mean they should use UN and KL rather than Pangea in the iMac/iBook in the future? If so, what would be the point?
Bye,
RazzFazz
[ 03-30-2002: Message edited by: RazzFazz ]</p>
<strong>[qb]Originally posted by Amorph:
The only thing I can think of is that, in the embedded markets, the off-chip cache often is the system RAM, and there is sufficient demand in that market for DDR SDRAM L3 cache. Meanwhile, for system communications, the MaxBus/60x bus architecture was considered adequate.</strong>
Perhaps. If true, more reason for Apple to take PPC processor design in-house.
<strong>Aside from the obvious problems (shorter traces, interference problems, higher sensitivity, etc.) what would make a clock-doubled bus difficult on the G4? Anyone?</strong>
I can't think of a thing.
[quote]
Posted by Amorph:
It seems that the MaxBus does a lot of delicate work in order to use its bandwidth efficiently and reduce latency; does that make it difficult (or expensive, or both) to double the clock and preserve backward compatibility?
<strong>The clock isn't doubled. All PC2100 RAM operate at 133 MHz clock rate just like PC133 does. It's double data rate, sort of like AGP 2x. Data can be sent on the rising and falling edges of the sinusoidal clock signal, and therefore double its theoretical data rate.</strong><hr></blockquote>
Oof.
What I meant was, would there be a large number of problems inherent in taking an efficient SDR bus architecture to DDR? Has anyone ever tried, or is it more common to just design a new bus around DDR?
<strong>
What I meant was, would there be a large number of problems inherent in taking an efficient SDR bus architecture to DDR? Has anyone ever tried, or is it more common to just design a new bus around DDR?</strong><hr></blockquote>
Well, at least the Athlon's DDR and the P4's QDR bus were completely designs AFAIU.
Dunno for the bus between northbridge and RAM modules, though.
Bye,
RazzFazz
"10% to 20% gain doesn't seem worth it. Apple is probably on the right track with DDR "<hr></blockquote>
In the summary of the Tom's Hardware article you linked to, this is what the author had to say," [quote]The introduction of DDR SDRAM is indeed an impressive thing. Performance gains of over 10% are worth a lot of respect. We have never seen anything like that ever before with any other new memory type.<hr></blockquote>
just the Tom's Hardware author's 2 cents
<strong>
just the Tom's Hardware author's 2 cents</strong><hr></blockquote>
In terms of memory speed, it is a big thing. In terms of overall computer speed I think a lot of people assume that double data rate (DDR) means the computer will be twice as fast, au contraire, most users woudn't see any difference... so why should apple add this feature to the legacy G4 if new processors are coming out. In fact, I think the fact that Apple does not try to get Moto to make DDR possible means that indeed a new chip (and new motherboard) is on the horizon (duh). If it were me, I would make a new motherboard that will work with the G4 and what ever the new chip will be called.
Question will always be when.
I'm no expert, but it's probably only now that the G4 is really starting to feel the effects of the slow memory bus, not a year ago.
[ 03-31-2002: Message edited by: Bozo the Clown ]</p>