Its not really all that "good stuff"... none of them are 7455 optimized, and none of the RAM moving tests are even AltiVec optimized (except the one to the video card, which doesn't really count but does show >900 in one case). Proper use of the AltiVec streaming instructions is key to optimal memory throughput on these machines.
Optimized memory moves are a bit tricky to get right, and not all 133 MHz SDRAM is created equal. I'm not up on all the terminology and details, but you can put either CL3 or CL2 SDRAM onto your motherboard and this will impact performance significantly.</strong><hr></blockquote>
Just to get things straight, I take it that DDR RAM relies heavily on a very good compiler and a great API. It seems to me that misses and data being out of order really limit performance. So there is a greater burden in getting the data lined up and ensuring that it all flows well or the through put numbers really suffer. Is this correct??
<strong>128bit busses would have been possible since the introduction of the G4, Arstechnica actually said it was sad they didn't go for 128bit. But it was a very clever move of Apple NOT to go 128bit, because we're already bitching about high prices...a 128bit mobo would have taken us far beyong the 5000$ mark I'd say, and frankly nobody is ready to pay such an amount of money today. People buy computers for 1000 and 2000$, and with 3000 we're already clearly above that level.
Also 128bit bus would only make sense if you had 128bit memory or interleaved dual bank 64bit memory, which would again add costs.
I'm looking forward to seeing what Apple has cooked up this time.
G-News</strong><hr></blockquote>
Where did you get that a 128 bit mobo will cost so much : far beyond 5000 $. 128 bit bus already exist it is the nvidia nforce mobo sell under 200 $.
Just to get things straight, I take it that DDR RAM relies heavily on a very good compiler and a great API. It seems to me that misses and data being out of order really limit performance. So there is a greater burden in getting the data lined up and ensuring that it all flows well or the through put numbers really suffer. Is this correct??</strong><hr></blockquote>
You can get around this with lots of registers and good, fast caches, which are made for handling repeated references to small blocks of data.
But then, it's also up to the compiler to use those efficiently, so yes, the compiler is really crucial.
What kind of memory does nForce use?? Where do I find out more??</strong><hr></blockquote>
I can answer mown question, from the nForce official sight.
"TwinBank Memory Architecture
As more and more computer users run more complex 3D applications, the need for system memory bandwidth increases. Why? Well, a 3D application, such as Quake III, runs at high resolutions, high color depths, high frame rates, and high refresh rates?which overall means a stunning gaming experience, but one that requires valuable system memory bandwidth. Before the nForceTM SPP/IGP and its TwinBankTM Memory Architecture, high-performance processing with a CPU and an integrated GPU just wasn't possible?leaving PC manufacturers with one choice: deliver an inexpensive solution that provided only limited system performance and sub-par graphics.
What is TwinBank and Why is it Important?
The patent-pending TwinBank Memory Architecture, an innovative 128-bit memory controller supporting DDR-266MHz system memory technologies, was designed to achieve optimal system and graphics performance, and provide the highest memory bandwidth possible. Only with TwinBank, can you perform concurrent tasks without any performance degradation, including:
checking e-mail,
browsing the Web,
watching DVD movies,
and playing 3D-intensive games.
Unequivocally, TwinBank forms the performance foundation for NVIDIA's nForce Platform Processing Architecture, giving users the ability to run multiple applications simultaneously without having to worry about memory bandwidth or performance slowdowns.
The TwinBank Solution
Fully scalable, with support for a wide variety of memory configurations, TwinBank's dual-independent, cross-bar memory controller allows the CPU and the graphics and audio subsystems simultaneous access to the system's 4.2GB/sec. of memory bandwidth, guaranteeing continuous access for all applications, all the time. In fact, in tests TwinBank delivered up to 30% peak system memory bandwidth when compared to comparable dual-channel-based RDRAM chipsets. Unlike other systems utilizing a multiple arbitration process, TwinBank was designed around a single-step arbiter, reducing system latency and improving overall system performance even more.
The days of mediocre system performance are now over. With the NVIDIA nForce SPP/IGP and its revolutionary TwinBank Memory Architecture, exceptional system performance is available at all times. TwinBank allows PC users to simultaneously run multiple 2D and 3D applications without any loss in system performance, speed, or functionality."
There are a couple of things to take away from this initial performance measurement. According to Sandra, the nForce 420-D only offers 26MB/s more useable memory bandwidth than the VIA KT266A. This is in spite of the fact that the 420-D has twice the theoretical memory bandwidth of the KT266A. The explanation is obvious and not too shocking; the Athlon is limited by its FSB in that the IGP can only get 2.1GB/s of data to it at any given time so having 4.2GB/s of memory bandwidth isn't all that useful.
Apple pretty much has the same problem. They control the memory controller, but the processor bus is Moto's baby.
Apple pretty much has the same problem. They control the memory controller, but the processor bus is Moto's baby.[/QB]<hr></blockquote>
"The RapidIO Interconnect Architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a high-performance, packet-switched, interconnect technology. It addresses the high-performance embedded industry's need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. The RapidIO interconnect allows chip-to-chip and board-to-board communications at performance levels scaling to ten Gigabits per second and beyond."
Addressing the needs for higher compute density and lower system cost, the Motorola MPC8540 integrated host processor is designed to provide the highest level of performance and integration available today. The MPC8540 is Motorola's first device utilizing the e500 core; is the industry's first RapidIO-enabled processor; and provides dual gigabit ethernet controllers. Balancing processor performance with I/O system throughput, the MPC8540 is a powerful control element for network routers and switches, storage subsystems, network appliances, and print and imaging devices.
MPC8540 Features
Innovative Technology
The MPC8540 processor integrates IEEE 802.3 10/100/1G Ethernet controllers (with support for jumbo frames and Layer 2 acceleration), a 10/100 controller, a 64-bit PCI-X controller operating at up to 133MHz, a DDR memory controller, a 4-channel DMA, a multi-channel interrupt controller, and a DUART serial interface. Its high level of integration means simplified board design, lower power consumption and a faster time-to-market solution for customers.
The MPC8540 also integrates the e500 core, 256KB of on-chip L2 cache, and the revolutionary on-chip non-blocking crossbar switch fabric, called OCeaN (On-Chip Network), allowing for full duplex port connections at 128Gb/s concurrent throughput and independent per port transaction queuing and flow control.I just like the sound of that. <img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
e500 Core
Utilizing an SoC platform which balances MIPs, watts, packet performance and cost, Motorola has created a flexible platform architecture enabling multiple products from easily integrated IP. The e500 high performance core implements the enhanced PowerPC Book E instruction set architecture and provides unprecedented levels of hardware and software debug support. The e500 will serve as the core for a family of ASSPs for communications, automotive and consumer applications.
RapidIO Interconnect
As a founding member of the RapidIO Trade Association, Motorola has been driving the industry adoption of this new, high-performance switch fabric control plane interconnect. RapidIO offers significantly greater bandwidth, scalability and reliability than interconnects used today, yet is compatible with existing PCI and CPU architectures. It has a flexible architecture that can easily adapt to changing industry needs without affecting existing infrastructure. RapidIO is an open standard governed by an industry body, designed specifically for embedded, networking and communications applications.
I know this is not news to this forum but I thought that it was relevant to the discussion.
<strong>nForce is based on Hypertransport, which is again an entirely different story.
Were talking about 128bit MaxBus here.
G-News</strong><hr></blockquote>
128 bit maxbus need a new chip, the current chip is only a 64 bit wide controller. Hypertransport or not the nforce is 128bit wide, but the athlon is 64 bit limited.
And i don't change my mind, 2000 $ more for 128 bit wide is a joke.
This is just a guess, but I think there is a possibility that the new eMac and this new rackmount server may share motherboards. The question is what market is Apple going for with this server? Is it a web server, file server, part of a render farm. If Apple wanted to kill two birds with one stone, take the eMac's innards, put them in that sleek pizza box case, and sell it for $899. It would be a great cheap server, and the headless iMac we have all been waiting for. Likewise Apple could introduce a high-end server with the new DDR motherboard and market this as a powerful, render farm server. What do you think?
<strong><snip> The question is what market is Apple going for with this server?
<snip>Is it a web server, file server, part of a render farm. What do you think?</strong><hr></blockquote>
I would think that Apple would be going after the render farm market since they bought UnReal. But you make a valid point, they don't need alot of power to file serve. They may eventually come out with both kinds of rack mounts, file server for now and renderer later. This would make sense because this would allow them to get manufacturing bugs worked out. However if they have the goods they could ship a high powered version now and Avid, FCP, and Maya would be the demanding software. It looks like the high-end version has more need right now, but I wouldn't put it past them to start small in May and go high-end in July.
While I have no idea what this server will be for, what I would like to happen is SJ to introduce a hi end kick ass render farm server, and then do a "one more thing" and introduce the cheap file server/pizza box version with the same case. Exact same case, different mb. Take the eMac MB, add ADC and a full size VGA port, and market it as cheap file server. While many people will buy it for that purpose, poor college students (such as myself) buy this as a really cheap mac. The new eMac/iMac is nice, but too expensive. I already have a nice vga display, and I cannot afford a new flat panel. I don't need PCI, I don't need AGP, just cheap and powerful. This form factor looks cool (reminds me of the old NeXt slab). It would add that dirt cheap, geek box that people like ourselves have been clamoring for. Apple should exploit this opportunity.
Sorry for answering both questions, didn't know I could find this.
MPC8540 : Integrated Host Processor
...
The MPC8540 also integrates the e500 core, 256KB of on-chip L2 cache, and the revolutionary on-chip non-blocking crossbar switch fabric, called OCeaN (On-Chip Network), allowing for full duplex port connections at 128Gb/s concurrent throughput and independent per port transaction queuing and flow control.I just like the sound of that. <img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
RapidIO Interconnect
...
I know this is not news to this forum but I thought that it was relevant to the discussion.</strong>
We've known it since it was announced last November. The problem is that it is not shipping, and won't ship until Q4 2002. This is just a problem for speculation and debate, not that important.
The real problem is that by the time this thing ships, every single one of Apple's G4 (and G3 if the iBook has G3s) computers will have processors that are faster than this chip. Apple has been shipping a processor this fast in its Power Macs for 4 months.
does anyone think that Apple will include a 'special' technology to make getting an Apple Rackmount that much more interesting? Yeah, sure, its OS Server and G4/G5 chips... but I hardly think that would make many people REALLY want to go out and get them.
I really think Apple is going to include somekind of Mac-only technology that will get the geeks drooling and the big bucks flowing.
At least I would think they would.
Gigawire interconnects... blah barely a high-point. Anything else it could be?
Comments
TING5
<strong>
Its not really all that "good stuff"... none of them are 7455 optimized, and none of the RAM moving tests are even AltiVec optimized (except the one to the video card, which doesn't really count but does show >900 in one case). Proper use of the AltiVec streaming instructions is key to optimal memory throughput on these machines.
Optimized memory moves are a bit tricky to get right, and not all 133 MHz SDRAM is created equal. I'm not up on all the terminology and details, but you can put either CL3 or CL2 SDRAM onto your motherboard and this will impact performance significantly.</strong><hr></blockquote>
Just to get things straight, I take it that DDR RAM relies heavily on a very good compiler and a great API. It seems to me that misses and data being out of order really limit performance. So there is a greater burden in getting the data lined up and ensuring that it all flows well or the through put numbers really suffer. Is this correct??
<strong>128bit busses would have been possible since the introduction of the G4, Arstechnica actually said it was sad they didn't go for 128bit. But it was a very clever move of Apple NOT to go 128bit, because we're already bitching about high prices...a 128bit mobo would have taken us far beyong the 5000$ mark I'd say, and frankly nobody is ready to pay such an amount of money today. People buy computers for 1000 and 2000$, and with 3000 we're already clearly above that level.
Also 128bit bus would only make sense if you had 128bit memory or interleaved dual bank 64bit memory, which would again add costs.
I'm looking forward to seeing what Apple has cooked up this time.
G-News</strong><hr></blockquote>
Where did you get that a 128 bit mobo will cost so much : far beyond 5000 $. 128 bit bus already exist it is the nvidia nforce mobo sell under 200 $.
Were talking about 128bit MaxBus here.
G-News
<strong>
Just to get things straight, I take it that DDR RAM relies heavily on a very good compiler and a great API. It seems to me that misses and data being out of order really limit performance. So there is a greater burden in getting the data lined up and ensuring that it all flows well or the through put numbers really suffer. Is this correct??</strong><hr></blockquote>
You can get around this with lots of registers and good, fast caches, which are made for handling repeated references to small blocks of data.
But then, it's also up to the compiler to use those efficiently, so yes, the compiler is really crucial.
<strong>nForce is based on Hypertransport, which is again an entirely different story.
Were talking about 128bit MaxBus here.
G-News</strong><hr></blockquote>
Apple is a player on the Hypertransport group. What kind of memory does nForce use?? Where do I find out more??
What's your guess?
eMac is for education
iMac is for consumers
PowerMac is for prosumers/professionals
?? for entreprise/IT customers
<strong>
What kind of memory does nForce use?? Where do I find out more??</strong><hr></blockquote>
I can answer mown question, from the nForce official sight.
"TwinBank Memory Architecture
As more and more computer users run more complex 3D applications, the need for system memory bandwidth increases. Why? Well, a 3D application, such as Quake III, runs at high resolutions, high color depths, high frame rates, and high refresh rates?which overall means a stunning gaming experience, but one that requires valuable system memory bandwidth. Before the nForceTM SPP/IGP and its TwinBankTM Memory Architecture, high-performance processing with a CPU and an integrated GPU just wasn't possible?leaving PC manufacturers with one choice: deliver an inexpensive solution that provided only limited system performance and sub-par graphics.
What is TwinBank and Why is it Important?
The patent-pending TwinBank Memory Architecture, an innovative 128-bit memory controller supporting DDR-266MHz system memory technologies, was designed to achieve optimal system and graphics performance, and provide the highest memory bandwidth possible. Only with TwinBank, can you perform concurrent tasks without any performance degradation, including:
checking e-mail,
browsing the Web,
watching DVD movies,
and playing 3D-intensive games.
Unequivocally, TwinBank forms the performance foundation for NVIDIA's nForce Platform Processing Architecture, giving users the ability to run multiple applications simultaneously without having to worry about memory bandwidth or performance slowdowns.
The TwinBank Solution
Fully scalable, with support for a wide variety of memory configurations, TwinBank's dual-independent, cross-bar memory controller allows the CPU and the graphics and audio subsystems simultaneous access to the system's 4.2GB/sec. of memory bandwidth, guaranteeing continuous access for all applications, all the time. In fact, in tests TwinBank delivered up to 30% peak system memory bandwidth when compared to comparable dual-channel-based RDRAM chipsets. Unlike other systems utilizing a multiple arbitration process, TwinBank was designed around a single-step arbiter, reducing system latency and improving overall system performance even more.
The days of mediocre system performance are now over. With the NVIDIA nForce SPP/IGP and its revolutionary TwinBank Memory Architecture, exceptional system performance is available at all times. TwinBank allows PC users to simultaneously run multiple 2D and 3D applications without any loss in system performance, speed, or functionality."
4.2 GB/sec, 266 DDR
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" /> Wow <img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
[ 05-08-2002: Message edited by: Brendon ]</p>
... NVIDIA nForce SPP/IGP and its revolutionary TwinBank Memory Architecture ...
4.2 GB/sec, 266 DDR
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" /> Wow <img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
</strong>
Unfortunately, since the Athlons only have a 2.1 GByte/sec processor bus, the TwinBank memory architecture is fairly <a href="http://anandtech.com/chipsets/showdoc.html?i=1535&p=1"; target="_blank">useless</a>.
There are a couple of things to take away from this initial performance measurement. According to Sandra, the nForce 420-D only offers 26MB/s more useable memory bandwidth than the VIA KT266A. This is in spite of the fact that the 420-D has twice the theoretical memory bandwidth of the KT266A. The explanation is obvious and not too shocking; the Athlon is limited by its FSB in that the IGP can only get 2.1GB/s of data to it at any given time so having 4.2GB/s of memory bandwidth isn't all that useful.
Apple pretty much has the same problem. They control the memory controller, but the processor bus is Moto's baby.
Apple pretty much has the same problem. They control the memory controller, but the processor bus is Moto's baby.[/QB]<hr></blockquote>
"The RapidIO Interconnect Architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a high-performance, packet-switched, interconnect technology. It addresses the high-performance embedded industry's need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. The RapidIO interconnect allows chip-to-chip and board-to-board communications at performance levels scaling to ten Gigabits per second and beyond."
Don't Moto make a chip with RapidIO
<strong>
Don't Moto make a chip with RapidIO</strong><hr></blockquote>
Sorry for answering both questions, didn't know I could find this.
From Motos embedded communications chip sight:
<a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=02M0ylfVS0lM0 ypLRtk6" target="_blank">http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=02M0ylfVS0lM0 ypLRtk6</a>
MPC8540 : Integrated Host Processor
Addressing the needs for higher compute density and lower system cost, the Motorola MPC8540 integrated host processor is designed to provide the highest level of performance and integration available today. The MPC8540 is Motorola's first device utilizing the e500 core; is the industry's first RapidIO-enabled processor; and provides dual gigabit ethernet controllers. Balancing processor performance with I/O system throughput, the MPC8540 is a powerful control element for network routers and switches, storage subsystems, network appliances, and print and imaging devices.
MPC8540 Features
Innovative Technology
The MPC8540 processor integrates IEEE 802.3 10/100/1G Ethernet controllers (with support for jumbo frames and Layer 2 acceleration), a 10/100 controller, a 64-bit PCI-X controller operating at up to 133MHz, a DDR memory controller, a 4-channel DMA, a multi-channel interrupt controller, and a DUART serial interface. Its high level of integration means simplified board design, lower power consumption and a faster time-to-market solution for customers.
The MPC8540 also integrates the e500 core, 256KB of on-chip L2 cache, and the revolutionary on-chip non-blocking crossbar switch fabric, called OCeaN (On-Chip Network), allowing for full duplex port connections at 128Gb/s concurrent throughput and independent per port transaction queuing and flow control. I just like the sound of that. <img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
e500 Core
Utilizing an SoC platform which balances MIPs, watts, packet performance and cost, Motorola has created a flexible platform architecture enabling multiple products from easily integrated IP. The e500 high performance core implements the enhanced PowerPC Book E instruction set architecture and provides unprecedented levels of hardware and software debug support. The e500 will serve as the core for a family of ASSPs for communications, automotive and consumer applications.
RapidIO Interconnect
As a founding member of the RapidIO Trade Association, Motorola has been driving the industry adoption of this new, high-performance switch fabric control plane interconnect. RapidIO offers significantly greater bandwidth, scalability and reliability than interconnects used today, yet is compatible with existing PCI and CPU architectures. It has a flexible architecture that can easily adapt to changing industry needs without affecting existing infrastructure. RapidIO is an open standard governed by an industry body, designed specifically for embedded, networking and communications applications.
I know this is not news to this forum but I thought that it was relevant to the discussion.
Don't Moto make a chip with RapidIO</strong>
Not yet. Q4 02 if Moto meets its schedule. This is also on a chip that's useless to Apple.
<strong>nForce is based on Hypertransport, which is again an entirely different story.
Were talking about 128bit MaxBus here.
G-News</strong><hr></blockquote>
128 bit maxbus need a new chip, the current chip is only a 64 bit wide controller. Hypertransport or not the nforce is 128bit wide, but the athlon is 64 bit limited.
And i don't change my mind, 2000 $ more for 128 bit wide is a joke.
I have seen a pretty cool integrated water cooling solution - properitary though, but very professional.
Will we see different variants? A return of the cube formfactor for home use?
<strong><snip> The question is what market is Apple going for with this server?
<snip>Is it a web server, file server, part of a render farm. What do you think?</strong><hr></blockquote>
I would think that Apple would be going after the render farm market since they bought UnReal. But you make a valid point, they don't need alot of power to file serve. They may eventually come out with both kinds of rack mounts, file server for now and renderer later. This would make sense because this would allow them to get manufacturing bugs worked out. However if they have the goods they could ship a high powered version now and Avid, FCP, and Maya would be the demanding software. It looks like the high-end version has more need right now, but I wouldn't put it past them to start small in May and go high-end in July.
Good question!
Sorry for answering both questions, didn't know I could find this.
MPC8540 : Integrated Host Processor
...
The MPC8540 also integrates the e500 core, 256KB of on-chip L2 cache, and the revolutionary on-chip non-blocking crossbar switch fabric, called OCeaN (On-Chip Network), allowing for full duplex port connections at 128Gb/s concurrent throughput and independent per port transaction queuing and flow control. I just like the sound of that. <img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
RapidIO Interconnect
...
I know this is not news to this forum but I thought that it was relevant to the discussion.</strong>
We've known it since it was announced last November. The problem is that it is not shipping, and won't ship until Q4 2002. This is just a problem for speculation and debate, not that important.
The real problem is that by the time this thing ships, every single one of Apple's G4 (and G3 if the iBook has G3s) computers will have processors that are faster than this chip. Apple has been shipping a processor this fast in its Power Macs for 4 months.
[ 05-09-2002: Message edited by: THT ]</p>
I really think Apple is going to include somekind of Mac-only technology that will get the geeks drooling and the big bucks flowing.
At least I would think they would.
Gigawire interconnects... blah barely a high-point. Anything else it could be?