People keep quoting this, but it is bullsh!t !!! The 10-15% quote refers to overall system performance resulting from a doubling of memory bandwidth. Since the measured tasks were not memory bound, their performance did not scale with the increase in memory bandwidth.
Memory bandwidth on a 166 MHz MPX bus will be about 1.25 GB/sec, a far cry from the 2.1 GB/sec of a 133 MHz DDR bus.
For what its worth, I read the comment from Motorola elsewhere as well -- and I believe it. It just makes too much sense. There are three ways out of this situation (assuming Moto is building the chip):
1) A specialized development just for Apple.
2) A PPC using MPX and an on-chip memory controller.
3) A PPC using RapidIO and an on-chip memory controller.
#1 is unlikely. #2 could happen in a shorter time frame than #3, but would just be a stop-gap and I don't expect to see it. #3 has been rumoured for some time now, but most of the rumours place it in Jan'03. This doesn't have to be a G5 as the existing core of the G4 could be used with it.
No cause for optimism, but nonetheless I remain hopeful that what ships in July will improve the current situation significantly.</strong><hr></blockquote>
I completely understand the problem with the G4 bandwidth being locked at 1ghz . My point was DDR isn't the answer all and a mpx bus at 166 would probably be better than DDR. This of course assumes that the G4 had available bandwidth to use it.
<strong>If its not a G5 then what the hell does any of this matter anyway?
Oooh! a g4 that's 20% faster than the last one! - Whoop de doo!! </strong><hr></blockquote>
hehe. You realise 20% actual speed gain in a computer in one release isn't too bad although I would expect a little better come July.
People are so caught up in the G5 will be a wonderful superchip created from nothing. I believe you will find it is just a G4 that has been evolved to fix faults, improve certain features and include a few new features.
Doing each of those things just bumps performance a little.
People keep quoting this, but it is bullsh!t !!! The 10-15% quote refers to overall system performance resulting from a doubling of memory bandwidth. Since the measured tasks were not memory bound, their performance did not scale with the increase in memory bandwidth.
Memory bandwidth on a 166 MHz MPX bus will be about 1.25 GB/sec, a far cry from the 2.1 GB/sec of a 133 MHz DDR bus.
For what its worth, I read the comment from Motorola elsewhere as well -- and I believe it. It just makes too much sense. There are three ways out of this situation (assuming Moto is building the chip):
1) A specialized development just for Apple.
2) A PPC using MPX and an on-chip memory controller.
3) A PPC using RapidIO and an on-chip memory controller.
#1 is unlikely. #2 could happen in a shorter time frame than #3, but would just be a stop-gap and I don't expect to see it. #3 has been rumoured for some time now, but most of the rumours place it in Jan'03. This doesn't have to be a G5 as the existing core of the G4 could be used with it.
No cause for optimism, but nonetheless I remain hopeful that what ships in July will improve the current situation significantly.</strong><hr></blockquote>
There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.
There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.</strong><hr></blockquote>
<strong>There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.</strong><hr></blockquote>
the lines from Bad Andy are a cold shower for me... NO DDR FSB !
"The bummer is that all the vibes coming out of moto and other competent sources are that the MPXbus will NOT get anything like the overhaul needed to go to DDR rates. The line from Raj Handa (PPC marketing at Moto) is that MPXbus will remain an SDR bus with a possible boost to 166 MHz SDR ... It is a complex hardware explanation to go through the issues; but basically most of the communication market (which is Moto's absolutely core market for PPC) resolutely loves MPXbus the way it is and has a huge commitment of devices built for it. They really like being able to "glue" their comm-widget du jour right to the CPU's FSB."
Increasing at 20% intervals, it would take 4 such increases to double. Moore's law predicts doubling every 18 months(and its accurate for x86 at least), so for Apple to keep up they'd need to do those increases every 4.5 months - not just at the MacWorlds.
after some RDF mood... i think that we will see a DDR FSB at NY, Bad Andy and the guy at moto are wrong... cuz it's not possible that the G4 iMac or the PowerBook are staying with a SDR FSB for all of their lifetime or maybe ??? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
<strong>There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.</strong><hr></blockquote>
I was speaking about a world where Motorola wasn't taking the MPX bus to DDR... this is what the Moto PPC rep has said, and the reasons he gave are valid -- the MPX bus is not intended to be a point-to-point bus like the Athlon / PIV FSB. Given this data point, I came up with the above three alternatives.
<strong>I completely understand the problem with the G4 bandwidth being locked at 1ghz . My point was DDR isn't the answer all and a mpx bus at 166 would probably be better than DDR. This of course assumes that the G4 had available bandwidth to use it.</strong><hr></blockquote>
A 166 MHz bus would be a ~25% increase in bandwidth. DDR would be a 100% increase in bandwidth. In what way is the 166 MHz bus "probably better"??
The problem from (Apple's viewpoint) is that Motorola is building the G4 for the embedded market. In this space the MPX bus excels, but it also precludes the move to DDR.
<strong>after some RDF mood... i think that we will see a DDR FSB at NY, Bad Andy and the guy at moto are wrong... cuz it's not possible that the G4 iMac or the PowerBook are staying with a SDR FSB for all of their lifetime or maybe ??? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> </strong><hr></blockquote>
It is all too possible.
There are other solutions possible, however, which is what I was describing above.
Ranting about what specs I hope to see is pointless.
New, innovative solutions to problems is where its at. Think ATi's "Truform". Think G5 class CPUs modular cores. Think on-chip memory controllers. Think RapidIO, where you have (if I understand it correctly) basically a high-speed, switched network on your motherboard.
Its nice to be faster than the competition in specs. But Apple's motto is "Think Different". Lets see architecture which "Thinks Different". There is some funky **** in Apple's motherboards already (single integrated controller, sawtooth). Bring it on!
I'm really exicted by Motorola's 8540, the Book E core and RapidIO. A new approach to CPU families, and a new approach to internal buses.
<strong>Increasing at 20% intervals, it would take 4 such increases to double. Moore's law predicts doubling every 18 months(and its accurate for x86 at least), so for Apple to keep up they'd need to do those increases every 4.5 months - not just at the MacWorlds.</strong><hr></blockquote>
Moore's law doesn't predict a doubling in performance every 18 months it predicts a doubling in transistor density. Big difference.
Apple prefer bigger leaps less often while the PC world perfer constant updates. Apple fell behind due to some lousy efforts by Motorola's fabs but in general their idea is sound.
It's also worth noting as processes get smaller Moore's law starts to fail. Originally it was every 12 months it doubled then they changed it. Some law <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
The L 3 backside cache on the MPC7455 is DDR and, if I have read the documention correctly, it communicates on a DDR bus. Doesn't this imply that there is already some kind of controller(re: specialized contoller) between the CPU and the backside cache already?
This also confuses me somewhat(actually quite a lot)-
If the bus between the ram and the cpu is DDR, what about between the controller and the rest of the computer. Are all the PCI cards DDR capable? If not, they(PCI cards) communicate over a say 133 MHz bus to the controller, then the controller communicates to the CPU and ram using DDR? huh
There aren't too many rumors in this thread. It's just a bunch of folks explaining why a rumor might be true or false. Even still, it's quite interesting reading, although who knows whether anything posted here is accurate. I'm just impatient for the "next big thing" to appear and I want to know what it is. By the way, barefeats.com had a special on the Powerbook G4/800. It actually beat out the 800MHz tower on many tasks, and thrashed the 800MHz iMac! Looks like I know what my next laptop will be...
<strong>By the way, barefeats.com had a special on the Powerbook G4/800. It actually beat out the 800MHz tower on many tasks, and thrashed the 800MHz iMac! Looks like I know what my next laptop will be...
A 166 MHz bus would be a ~25% increase in bandwidth. DDR would be a 100% increase in bandwidth. In what way is the 166 MHz bus "probably better"??
</strong><hr></blockquote>
Well, as you regularly state yourself, those are the theoretical peak numbers, which are never reached in real life.
Depending on the memory access patterns, 166SDR can indeed be faster than 133DDR if you have lot's of non-contiguous random accesses throughout memory (only data is transfered at twice the clock rate with DDR, whereas address transfers and the various time constants are still synched to the "normal" clock).
[quote]<strong>The problem from (Apple's viewpoint) is that Motorola is building the G4 for the embedded market. In this space the MPX bus excels, but it also precludes the move to DDR.</strong><hr></blockquote>
Well, from the Moto website, it seems like their long-term vision for the embedded space includes migrating to RapidIO and seperate on-chip memory controllers instead.
<strong>The L 3 backside cache on the MPC7455 is DDR and, if I have read the documention correctly, it communicates on a DDR bus. Doesn't this imply that there is already some kind of controller(re: specialized contoller) between the CPU and the backside cache already?
</strong><hr></blockquote>
Yes, but the cache controller and the MPX bus controller are independant of each other.
[quote]<strong>This also confuses me somewhat(actually quite a lot)-
If the bus between the ram and the cpu is DDR, what about between the controller and the rest of the computer. Are all the PCI cards DDR capable? If not, they(PCI cards) communicate over a say 133 MHz bus to the controller, then the controller communicates to the CPU and ram using DDR? huh
</strong><hr></blockquote>
Again, these are all independent of each other. In fact, you have to look at it like this:
CPU
|
northbridge-RAM
|
PCI
All the connections ("|" and "-") can be of different speed, and it's the northbridge's job to handle communications between them.
Comments
<strong>
People keep quoting this, but it is bullsh!t !!! The 10-15% quote refers to overall system performance resulting from a doubling of memory bandwidth. Since the measured tasks were not memory bound, their performance did not scale with the increase in memory bandwidth.
Memory bandwidth on a 166 MHz MPX bus will be about 1.25 GB/sec, a far cry from the 2.1 GB/sec of a 133 MHz DDR bus.
For what its worth, I read the comment from Motorola elsewhere as well -- and I believe it. It just makes too much sense. There are three ways out of this situation (assuming Moto is building the chip):
1) A specialized development just for Apple.
2) A PPC using MPX and an on-chip memory controller.
3) A PPC using RapidIO and an on-chip memory controller.
#1 is unlikely. #2 could happen in a shorter time frame than #3, but would just be a stop-gap and I don't expect to see it. #3 has been rumoured for some time now, but most of the rumours place it in Jan'03. This doesn't have to be a G5 as the existing core of the G4 could be used with it.
No cause for optimism, but nonetheless I remain hopeful that what ships in July will improve the current situation significantly.</strong><hr></blockquote>
I completely understand the problem with the G4 bandwidth being locked at 1ghz . My point was DDR isn't the answer all and a mpx bus at 166 would probably be better than DDR. This of course assumes that the G4 had available bandwidth to use it.
Oooh! a g4 that's 20% faster than the last one! - Whoop de doo!!
<strong>If its not a G5 then what the hell does any of this matter anyway?
Oooh! a g4 that's 20% faster than the last one! - Whoop de doo!!
hehe. You realise 20% actual speed gain in a computer in one release isn't too bad although I would expect a little better come July.
People are so caught up in the G5 will be a wonderful superchip created from nothing. I believe you will find it is just a G4 that has been evolved to fix faults, improve certain features and include a few new features.
Doing each of those things just bumps performance a little.
<strong>
People keep quoting this, but it is bullsh!t !!! The 10-15% quote refers to overall system performance resulting from a doubling of memory bandwidth. Since the measured tasks were not memory bound, their performance did not scale with the increase in memory bandwidth.
Memory bandwidth on a 166 MHz MPX bus will be about 1.25 GB/sec, a far cry from the 2.1 GB/sec of a 133 MHz DDR bus.
For what its worth, I read the comment from Motorola elsewhere as well -- and I believe it. It just makes too much sense. There are three ways out of this situation (assuming Moto is building the chip):
1) A specialized development just for Apple.
2) A PPC using MPX and an on-chip memory controller.
3) A PPC using RapidIO and an on-chip memory controller.
#1 is unlikely. #2 could happen in a shorter time frame than #3, but would just be a stop-gap and I don't expect to see it. #3 has been rumoured for some time now, but most of the rumours place it in Jan'03. This doesn't have to be a G5 as the existing core of the G4 could be used with it.
No cause for optimism, but nonetheless I remain hopeful that what ships in July will improve the current situation significantly.</strong><hr></blockquote>
There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.
<strong>
There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.</strong><hr></blockquote>
I'll take two to go.
[quote] Just a quick ?...
is a 200MHz FSB == to a 100MHz FSB double-pumped (200Mhz effective)?
IE is it better to have DDR then SDR if they are both running at the same (effective) speeds? <hr></blockquote>
<strong>There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.</strong><hr></blockquote>
the lines from Bad Andy are a cold shower for me... NO DDR FSB !
"The bummer is that all the vibes coming out of moto and other competent sources are that the MPXbus will NOT get anything like the overhaul needed to go to DDR rates. The line from Raj Handa (PPC marketing at Moto) is that MPXbus will remain an SDR bus with a possible boost to 166 MHz SDR ... It is a complex hardware explanation to go through the issues; but basically most of the communication market (which is Moto's absolutely core market for PPC) resolutely loves MPXbus the way it is and has a huge commitment of devices built for it. They really like being able to "glue" their comm-widget du jour right to the CPU's FSB."
<strong>There is another possibility. Keep the MPX bus, but make it double data rate. It would hence match the speed of the associated DDR memory.</strong><hr></blockquote>
I was speaking about a world where Motorola wasn't taking the MPX bus to DDR... this is what the Moto PPC rep has said, and the reasons he gave are valid -- the MPX bus is not intended to be a point-to-point bus like the Athlon / PIV FSB. Given this data point, I came up with the above three alternatives.
<strong>I completely understand the problem with the G4 bandwidth being locked at 1ghz . My point was DDR isn't the answer all and a mpx bus at 166 would probably be better than DDR. This of course assumes that the G4 had available bandwidth to use it.</strong><hr></blockquote>
<img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
A 166 MHz bus would be a ~25% increase in bandwidth. DDR would be a 100% increase in bandwidth. In what way is the 166 MHz bus "probably better"??
The problem from (Apple's viewpoint) is that Motorola is building the G4 for the embedded market. In this space the MPX bus excels, but it also precludes the move to DDR.
<strong>after some RDF mood... i think that we will see a DDR FSB at NY, Bad Andy and the guy at moto are wrong... cuz it's not possible that the G4 iMac or the PowerBook are staying with a SDR FSB for all of their lifetime or maybe ??? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> </strong><hr></blockquote>
It is all too possible.
There are other solutions possible, however, which is what I was describing above.
New, innovative solutions to problems is where its at. Think ATi's "Truform". Think G5 class CPUs modular cores. Think on-chip memory controllers. Think RapidIO, where you have (if I understand it correctly) basically a high-speed, switched network on your motherboard.
Its nice to be faster than the competition in specs. But Apple's motto is "Think Different". Lets see architecture which "Thinks Different". There is some funky **** in Apple's motherboards already (single integrated controller, sawtooth). Bring it on!
I'm really exicted by Motorola's 8540, the Book E core and RapidIO. A new approach to CPU families, and a new approach to internal buses.
Trés Chic
Barto
<strong>Increasing at 20% intervals, it would take 4 such increases to double. Moore's law predicts doubling every 18 months(and its accurate for x86 at least), so for Apple to keep up they'd need to do those increases every 4.5 months - not just at the MacWorlds.</strong><hr></blockquote>
Moore's law doesn't predict a doubling in performance every 18 months it predicts a doubling in transistor density. Big difference.
Apple prefer bigger leaps less often while the PC world perfer constant updates. Apple fell behind due to some lousy efforts by Motorola's fabs but in general their idea is sound.
It's also worth noting as processes get smaller Moore's law starts to fail. Originally it was every 12 months it doubled then they changed it. Some law <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
The L 3 backside cache on the MPC7455 is DDR and, if I have read the documention correctly, it communicates on a DDR bus. Doesn't this imply that there is already some kind of controller(re: specialized contoller) between the CPU and the backside cache already?
This also confuses me somewhat(actually quite a lot)-
If the bus between the ram and the cpu is DDR, what about between the controller and the rest of the computer. Are all the PCI cards DDR capable? If not, they(PCI cards) communicate over a say 133 MHz bus to the controller, then the controller communicates to the CPU and ram using DDR? huh
color me hopelessly confused.
[ 05-27-2002: Message edited by: rickag ]</p>
Matthew
<strong>By the way, barefeats.com had a special on the Powerbook G4/800. It actually beat out the 800MHz tower on many tasks, and thrashed the 800MHz iMac! Looks like I know what my next laptop will be...
</strong><hr></blockquote>
L3 is your friend
<strong>
A 166 MHz bus would be a ~25% increase in bandwidth. DDR would be a 100% increase in bandwidth. In what way is the 166 MHz bus "probably better"??
</strong><hr></blockquote>
Well, as you regularly state yourself, those are the theoretical peak numbers, which are never reached in real life.
Depending on the memory access patterns, 166SDR can indeed be faster than 133DDR if you have lot's of non-contiguous random accesses throughout memory (only data is transfered at twice the clock rate with DDR, whereas address transfers and the various time constants are still synched to the "normal" clock).
[quote]<strong>The problem from (Apple's viewpoint) is that Motorola is building the G4 for the embedded market. In this space the MPX bus excels, but it also precludes the move to DDR.</strong><hr></blockquote>
Well, from the Moto website, it seems like their long-term vision for the embedded space includes migrating to RapidIO and seperate on-chip memory controllers instead.
Bye,
RazzFazz
<strong>The L 3 backside cache on the MPC7455 is DDR and, if I have read the documention correctly, it communicates on a DDR bus. Doesn't this imply that there is already some kind of controller(re: specialized contoller) between the CPU and the backside cache already?
</strong><hr></blockquote>
Yes, but the cache controller and the MPX bus controller are independant of each other.
[quote]<strong>This also confuses me somewhat(actually quite a lot)-
If the bus between the ram and the cpu is DDR, what about between the controller and the rest of the computer. Are all the PCI cards DDR capable? If not, they(PCI cards) communicate over a say 133 MHz bus to the controller, then the controller communicates to the CPU and ram using DDR? huh
</strong><hr></blockquote>
Again, these are all independent of each other. In fact, you have to look at it like this:
CPU
|
northbridge-RAM
|
PCI
All the connections ("|" and "-") can be of different speed, and it's the northbridge's job to handle communications between them.
Bye,
RazzFazz
[ 05-27-2002: Message edited by: RazzFazz ]</p>
RapidIO is on Motorola's roadmap, so it's a good bet that in place of an MPX double pumped DDR frontside bus, the G4 or G5 will get a RapidIO bus.
The fact that Moto isn't going to make the MPX bus support DDR is a good thing. It means that something better will do it.