The AppleInsider Dictionary

Posted:
in General Discussion edited January 2014
I love Macs. I use them religiously, I promote them vigorously, and I dream of them constantly. Well, maybe those aren't quite true, but I do have quite a thing for the Mac platform.



Yet so much of the time, I feel like I don't speak the same language many of you do. With that in mind, let us start the AppleInsider dictionary. Please post any and all "techy" defintions you use on a regular basis that many of us less tech-orineted people can refer to.



I will start with a few words and concepts I do not fully understand:



- Maya

- Kernels in Mac OS X

- DDR RAM

- UMA 2

- 64-bit Processor

- Pipeline

- Backside/Front cache



Those are just a few to start. If you want a definition, ask! If you know it all, tell!



- Pook
«1

Comments

  • Reply 1 of 30
    cdhostagecdhostage Posts: 1,038member
    Tell me whether UMA 2 has been implemented in the QuickSilvers. What is UMA 2 and what does it mea for the Mac community?
  • Reply 2 of 30
    macaddictmacaddict Posts: 1,055member
    It would be great to have a FAQ for each forum, as Ars does.



    DDR RAM: RAM that can accomplish read and write functions at the same time in one clock cycle, in effect doubling the clock. So if your RAM is 133MHz but can read and write at the same time, it is effectively 266MHz. 100MHz DDR RAM is marketed as 200MHz. The DDR in DDR RAM stands for "double data rate".



    Pipeline: Usually I think people just say pipeline when they really mean pipeline stages. Most of the processors we use I'm pretty sure has one pipeline. Basically I think that instructions can go along faster with a longer pipeline, because at each stage less work is done. I think MHz is a measure of how fast the instructions move from stage to stage, but not how long it takes from start to finish. Not only may it take a processor with a long pipeline to finish an instruction, but if a "bad" instruction (I forget the technical term for them) gets in the pipeline has to be emptied and it takes longer for it to fill back up again. The performance at MWNY 01 was excellent at explaining all this. I have no clue what I'm talking about here so let's just wait until THT comes, yeah?



    Maya: 3D rendering software from Alias | Wavefront. Since the Mac has long been falling farther and farther behind in 3D markets, I think Apple hoped to catch up with the introduction of Maya that supposedly runs very well on a G4 with OS X. Costs thousands of dollars though, but sure looks cool.



    UMA 2: The motherboard design from Apple that would replace what we are currently using in the PowerMacs. Apple saves costs by using the same motherboard architecture in all of it's products (UMA stands for Unified Motherboard Architecture) and right now we're using UMA 1.5 or something. UMA 1 certainly exists, and the first product to use a motherboard sticking to UMA specifications was the iBook. UMA 1.5 and 2 could just be made up by the rumor mills for all we know, but UMA 2 designs will hopefully bring such goodies as DDR RAM and ATA 133.



    Backside/Front Cache: Backside cache is a very high speed memory that runs at half the speed of the processor (usually). Around half or a full megabyte in current G3 and G4 processors, it speeds up tasks by making commonly used data available right in the CPU at very high speed. I can't say I've heard of Front cache though. L1 maybe?



    64 bit processor: I am just learning about this too but from what I've read in the other thread it is a processor where data can be processed 64 bits at a time, as opposed to 32 bits at a time. Since current instructions are 32 bits, a recompile will be needed to take full advantage of a 64 bit CPU. Perhaps for a "true" 64 bit CPU the integer, FPU units etc. must all be 64 bit?



    Pretty much pure guesses on my part but okay.
  • Reply 3 of 30
    If y'all want to make a FAQ up... we'll be more than happy to host it and put it in the forum pages...
  • Reply 4 of 30
    daverdaver Posts: 496member
    Hmm, I'll take a shot at a couple of those.



    Maya

    Powerful 3-D modelling and animation application made by Alias|Wavefront. Long popular on Windows and Unix workstations, Maya was recently ported to Mac OS X. Maya is extremely expensive and compicated.



    UMA-2

    A term used to describe Apple's next-generation motherboard chipset, meaning "Unified Motherboard Architecture 2." UMA-2 is generally believed to include support for technologies like DDR-SDRAM, ATA-100 hard drives, 800 Mbps FireWire, and integrated 54 Mbps AirPort, although no one is entirely certain of an exact feature set. The term "UMA-2" dates back to at least January 2000 and has been the subject of far too much speculation. No one is really sure what it is, but we want it very badly.



    Quicksilver G4s are still based on a version of UMA popularly called "UMA-1.5" that was introduced in January 2001.



    Backside Cache

    First appearing with the PowerPC 750, backside cache is just level-2 cache that has a special bus for rapid communication with its processor. Backside cache can operate at the same speed as the processor, but more often operates at a fraction of this speed. Starting with the PowerPC 750CX and 7450, level-2 cache has been integrated directly on the processor, bumping backside cache (now used only on the 7450) to level-3.



    I hope this stuff is correct!
  • Reply 5 of 30
    eskimoeskimo Posts: 474member
    pipeline



    Pipelining is a technique employed by all modern desktop processors. It works by overlapping multiple instructions in execution. A very easy analogy is one of an assembly line. A pipeline is made up of stages, each stage performs a specific task on an instruction before sending the instruction forward to the next stage and receiving a new instruction from the previous stage. Pipelines when implemented properly are very effective. It allows for simulataneous work to be done on many instructions.



    My text in college used the example of doing laundry. Without pipelining you would do the following: Put dirty laundry in washer, when washer was finished move wet clothes to dryer, when dryer is finished place dry clothes on table and fold, after folded put away. Now if you approach this problem by using pipeling you can save time. Assuming you have 1 washer, 1 dryer, and 1 folder you are still only going to do one load at a time. But the time between each load being finished will be much less, especially for multiple loads. Now think that when the washer finishes the first load you move the clothes to the dryer, at the same time you put a new load in the washer. When the clothes come out of the dryer you fold them while putting wet load 2 into dryer and starting load 3 in washer and so on. It's more efficient.



    The problem occurs when you have what is known as a stall or bubble. To achieve maximum speed the processor is designed to basically make some guesses. When one of these guesses is wrong it has to go back and redo it. An example still using laundry would be a setting for normal or heavy duty wash on your washer. Suppose you had been doing 10 loads of laundry on normal which was fine. Say the 11th load was extremely soiled. Since the processor is trying to go as fast as possible it makes the decision that since the last 10 loads were normal this one probally is too and washes it on normal. But after it's removed from washer it's noticed that it isn't clean. Thus that load has to go back and be rewashed. Now if the person needs his favorite soccer jersey that was in that load the washing processor will have to clear everything else out in the line so that that load can be processed to keep the player from waiting. This is what is known as a stall and a pipeline flush.



    Most modern processors are also superscalar which means they have multiple pipelines capable of handling multiple instructions of the same type or different instructions in parallel with other pipelines. Traditionally each stage of the pipeline is tied to the clock. This clock expressed in cycles/second or Hertz is what people talk about when they say MHz or GHz. Think about being on an assembly line and having a bell ding every 5 seconds indicating you must pass your part onto the next person and receive a part from the person before you. That is similar to the clock which moves the instruction at the rise of each clock cycle.



    Backside/Frontside cache:



    Daver and MacAddict covered the backside cache definition well. What you call frontside cache was known on the mac as 'inline' cache. The frontside bus is the data communications pathway that lies on the motherboard of your computer and allows traffic between the CPU and the chipset. This frontside bus allows the CPU to fetch data from the main memory by asking the chipset for that information, the chipset then asks the memory to retrieve the information, it is sent to the chipset and from the chipset to the processor. The problem with this is that this takes a long time (relatively). To reduce this time, which is known as latency, engineers inserted a cache (cache is simply high speed low latency memory) between the chipset and the CPU. Thus if the CPU needed some information it could often find it in the relatively lower latency inline cache. The problem with this approach however was that the communication between the cache and the CPU reduced the aggregate bandwidth available for the main memory and other periphial connected through the chipset including IDE and PCI devices. Thus they gave the cache a bus of it's own on the 'backside' of the processor.
  • Reply 6 of 30
    I will start with a few words and concepts I do not fully understand:
    • Ryan Meader

    • That's pretty much it

  • Reply 7 of 30
    [quote]Ryan Meader<hr></blockquote>



    Nobody understands Ryan Meader



    [ 12-10-2001: Message edited by: DoctorGonzo ]</p>
  • Reply 8 of 30
    And it seems Meader is having a little touble with his site... iCab experiances a -3180 error when I try to load his page.
  • Reply 9 of 30
    Here's my contribution:



    This year I have to do a science project, which I am doing on Speech Recogniton. This my Background Research Paper (which I got a 98% on, BTW):



    NOTE: Please let me know what you think of it!

    [quote]



    Computer speech recognition is a very complex but interesting field of computer science. It requires logical thinking, understanding of how human speech works, and the ability to find solutions for very complex problems using computers. At the moment, speech recognition is not very advanced, but speech recognition will continue to improve as better ways of parsing (parse: to break down into more easily processed pieces of data) and understanding human speech are discovered. (Bernsen et al., 1998)



    Speech recognition starts by getting the sound of the user?s voice into the computer. This is done by digitizing the sound of the user speaking. After that, the computer must parse the signal to determine what is actually said. This may seem simple, but it is the hardest part of recognizing speech. Currently, the accepted method of doing this is by using phonemes. (Keller, 1994) Phonemes are the basic units of speech that represent one sound, like an ?ess? sound or a ?tee? sound. (Bernsen et al., 1998) The computer finds each phoneme and determines what sound was made. (McGraw-Hill Encyclopedia., 1995) It then combines the phonemes in each word and figures out what word was said by the user. (Stokes-Rees, date unknown) This information is then used by the computer to perform different tasks.



    The most simplistic speech software employs what is called ?Command and Control? speech recognition. This method of speech recognition uses a limited vocabulary of words and phrases that can be recognized and acted upon. If one is recognized, then the computer performs a specific task, such as opening a file or selecting a menu item.



    There are a number of uses for this type of speech recognition. One is controlling a computer, possibly for the handicapped. This type of interface is also sufficient in many automated situations, like getting flight information, where the vocabulary used is very small and the system is used for a specific purpose.



    The second method of speech recognition is called ?Dictation Recognition,? and often called the ?automatic typewriter.? This method of speech recognition requires a very large vocabulary compared to the Command and Control recognition. (Allen, 2000) This is because the computer should be able to recognize most of the words in the language it is used with. It must also be able to use context clues to figure out what word is said (an example of this is the use of the words to, too, and two).



    With this type of speech recognition, when the user says a word, the computer ?types? that word into a document. This is useful once again for the handicapped or for people who need to do two things at once, such as managing paperwork on their desks, or another activity that requires the person?s hands.



    The most complex method of speech recognition is what I have coined ?Comprehension Recognition?. This method of speech recognition is the ultimate goal of those in the field of speech recognition programs. (Schroeder, 1999) A computer using this level of speech recognition would need to have a large vocabulary, and must have a way of understanding what is said. This means it must be able to learn from past experiences and be able to think like a human, i.e., the computer would have artificial intelligence. (De Mori, 1998)



    A computer capable of this ability would not only be able to respond to what a user says, but be able to carry on an intelligent conversation with the user. It would be as if talking to a real person. This would be useful in many applications, such as direction giving, personal information managing programs, and automated tour guide computers.



    The experiment that will be performed for the purpose of this project will be a test of a dictation recognition software application, IBM ViaVoice for Mac OS X, to determine how much user voice training a dictation level speech recognition program will need to accurately understand a paragraph that is read to it. The hypothesis is that it will better understand what is said to it with the more training it receives. The independent variable will be the number of training sessions that are performed; the dependent variable will be the number of phrases that the computer mistakes. The computer will not be allowed learn from these mistakes, because we are testing the initial set up amount of training only, and not the gradual training the computer gets during normal usage.



    This project is unique in a number of respects. The project is in an area where not much information is available for it. This makes it hard to get many sources in the limited time available for research, so much of it must come from previous knowledge of the researcher. Also, it requires the use of a rather powerful computer (in this case, an Apple iBook G3 500 MHz) that can be demonstrated at the science fair.



    The main propose of this project is to determine how much training the software will need; which is the standard benchmark for speech recognition program testing. (Johnson, 2001) It does, however, provide insight into how advanced speech recognition programs are, and how little training can be necessary for a speech recognition program. It also demonstrates what kind of errors are common in speech recognition software.



    The project does have one particularly odd procedure in it. This odd procedure involves reinstalling the software (ViaVoice) after each set of data has been collected. This is to ensure that the program starts off with a fresh and clean database of the experimenter?s voice. (IBM Corp., 1999)



    Speech recognition is constantly evolving. It will continue to become more accurate, and will expand in its usefulness. Eventually it may be the most common way, if not the only way, to communicate with a computer. This is exciting. And at the rate that these advancements are going today, we might be talking to our computer sooner than we think.

    <hr></blockquote>



    [ 12-10-2001: Message edited by: graphiteman ]</p>
  • Reply 10 of 30
    macaddictmacaddict Posts: 1,055member
    Great explanation Eskimo.



    Now, what is the difference between a Northbridge and a Southbridge, and where do they connect to the processor?
  • Reply 11 of 30
    zozo Posts: 3,117member
    [quote]Originally posted by MacAddict:

    <strong>[b]

    Now, what is the difference between a Northbridge and a Southbridge, and where do they connect to the processor?</strong><hr></blockquote>



    from Sharkyextreme



    The northbridge communicates with the CPU over the Front Side Bus (FSB) and acts as the controller for memory, AGP and PCI. The type of FSB, memory and AGP varies from northbridge to northbridge. Some northbridges integrate video as well.



    The southbridge takes care of most basic forms of I/O, such as USB, serial ports, audio, IDE and more. What I/O is controlled depends on the specific southbridge. The southbridge sits on the northbridge's PCI bus, which is usually a 32-bit, 33MHz bus capable of providing 133MBps of bandwidth.

    --------------------------------



    The new Intel "Hub" Architecture and the "Hyper Transport" alliance are changing some of these things, but thats what it means traditionally.
  • Reply 12 of 30
    pscatespscates Posts: 5,847member
    Jeez, guys...how about keeping each FAQ UNDER 27 paragraphs and using plain English?







    I don't know anything more right now than I did 10 minutes ago.







    But the idea of a central glossary or FAQ for AppleInsider IS a great one, so do it, Jonathan (or whoever)!



    There should be a serious one, like above, that speaks to Mac terms and acronyms and technologies.



    THEN there should be one that's specific to AppleInsider and more of a fun one: explanations behind cats/watermelons, the whole MadTool episode, Murbot's ongoing ownership of every product Apple ever made, inside jokes (but then I guess they wouldn't be "inside", would they?), etc.



    [ 12-11-2001: Message edited by: pscates ]</p>
  • Reply 13 of 30
    gordygordy Posts: 1,004member
    I have one:
    • GigaWire

  • Reply 14 of 30
    cdhostagecdhostage Posts: 1,038member
    I have one



    Ginger



    Cuz obviously the scooter is not it. Dammit I want a Stirling engine!
  • Reply 15 of 30
    If y'all would like to compile an FAQ in HTML, we will host it. It won't be an official AI Project, but all those that help will be given recognition. Seriously guys, this is a great undertaking, and I think it's one of the best ideas ever for reducing a lot of the unnecessary, redundant posts asking what "xxx" is when someone mentions it in a discussion.



    Once again, put it into html, and we will host it.
  • Reply 16 of 30
    daverdaver Posts: 496member
    If anyone's interested in getting this done, I'll gladly help with the less technical stuff.
  • Reply 17 of 30
    A 64bit processor is a processor that can natively support a 64-bit memory address space.



    A 64bit processor also requires 64bit integers to compute with.



    The vast majority of software run has no need whatsoever for a 64bit processor. If you're running something that needs it, you know it and are already running it on such.



    64bit ISA's:

    Sun UltraSPARC

    DEC VAX

    DEC Alpha

    IBM POWER (NOT PowerPC*)

    SGI MIPS

    HP PA-RISC

    Intel/HP IA64



    Please note that these are the original developers. DEC sold the Alpha and VAX to Compaq and Compaq sold some IP to Intel; maybe the whole thing. The VAX is dead; the Alpha still has a few designs on the roadmap. Last order for VAX systems was taken over a year ago, possibly two.

    SGI has dead-ended the MIPS and HP has done the same for PA-RISC -- the PA-8900, which is due out in a year or two is the last design.



    HP originally developed IA64 and in 1993 presented it to Intel as PA-WW: Precision Architecture Wide Word. Intel and HP worked on it and officially announced it to the world as IA64 in 1996, I believe. IA64 is an EPIC ISA -- Explicitly Parallel Instruction Computing. The first IA64 chip is "Merced", which was officially named Itanium a couple of years ago. The second implementation is codenamed "McKinley" and will likely be officially called Itanium II or Itanium 2. It will go into pilot production sometime in 1Q02 and full production perhaps four to six months later.



    * = PowerPC, developed by IBM and Motorola, is a subset of the POWER ISA. It does not include 64bitness right off the bat, and it also doesn't include some of the other binaries and instructions. The ones it doesn't include are thoroughly useless for desktop computing; don't cry over them. Motorola will allegedly develop 64bit processors for Apple, but this will require a 64bit-aware version of OS X that will not run on any current or former Apple product.
  • Reply 18 of 30
    crusadercrusader Posts: 1,129member
    Kernels in Mac OS X-

    Well a kernel is the base of the operating system. It manages system memory, shares the processor, and other basic operating tasks. A kernel panic, according to apple is:





    [quote] A kernel panic is a type of error that occurs when the core (kernel) of an operating system receives an instruction in an unexpected format or that it fails to handle properly. When this happens in either Mac OS X 10.0 or Mac OS X Server, white text on a black background is drawn on top of the last video image on the monitor before the error occurred. A kernel panic may also follow when the operating system is not able to recover from a different type of error. A kernel panic can be caused by damaged or incompatible software or, more rarely, damaged or incompatible hardware. <hr></blockquote>
  • Reply 19 of 30
    sinewavesinewave Posts: 1,074member
    [quote]Originally posted by cdhostage:

    <strong>I have one



    Ginger



    Cuz obviously the scooter is not it. Dammit I want a Stirling engine!</strong><hr></blockquote>



    Yes the scooter = Ginger
  • Reply 20 of 30
    pookjppookjp Posts: 280member
    Here's another one:



    L2 and L3 cache.



    What are they? What's the difference? Which is better? Why?



    - Pook
Sign In or Register to comment.