Well if the "wires" all ran in one direction that would be true, but they actually run in 2 (and a half - multiple layers), so a thinner wire makes for closer wires in all dimensions that you are using.</strong><hr></blockquote>
While that is true remember that as mmcist pointed out a processor is limited by the speed of its transistors and the speed of its interconnects. Transistors are sped up by decreasing channel lengths, channel widths (the other dimension) are usually kept the same in order to provide increased current drive. The wider your pipe is the more current you can flow through it and force your capacitive transistors to transition.
Interconnects are similar, you want a low resistance path for your signals to travel. Therefore you want your metal lines to be as wide as possible while decreasing the length. Thus while you can increase your packing density by decreasing interconnect width it is a tradeoff with your electrical characteristics. Also as you increase the packing density of your metal lines by putting them closer together you increase the relative capacitance between the lines which also slows down your part. Capacitance is defined as being equal to k*A/t where k is your dielectric constant, A the area, and t your thickness. The spacing between metal lines can be viewed as t. So in order to counteract packing interconnects closer together you often look to lower your k value at the same time. This is the reason for all the research into low k dielectric materials currently in the semiconductor industry.
While that is true remember that as mmcist pointed out a processor is limited by the speed of its transistors and the speed of its interconnects. Transistors are sped up by decreasing channel lengths, channel widths (the other dimension) are usually kept the same in order to provide increased current drive. The wider your pipe is the more current you can flow through it and force your capacitive transistors to transition.
Interconnects are similar, you want a low resistance path for your signals to travel. Therefore you want your metal lines to be as wide as possible while decreasing the length. Thus while you can increase your packing density by decreasing interconnect width it is a tradeoff with your electrical characteristics. Also as you increase the packing density of your metal lines by putting them closer together you increase the relative capacitance between the lines which also slows down your part. Capacitance is defined as being equal to k*A/t where k is your dielectric constant, A the area, and t your thickness. The spacing between metal lines can be viewed as t. So in order to counteract packing interconnects closer together you often look to lower your k value at the same time. This is the reason for all the research into low k dielectric materials currently in the semiconductor industry.</strong><hr></blockquote>
Yes, a slightly fuller explanation than mine. Although I would add that as well as resistance limiting the dimensions of interconnects, electromigration limits how close interconnects can be to each other (especially at corners), this is a serious problem in current processes.
Yes, a slightly fuller explanation than mine. Although I would add that as well as resistance limiting the dimensions of interconnects, electromigration limits how close interconnects can be to each other (especially at corners), this is a serious problem in current processes.
Michael</strong><hr></blockquote>
Which is one of the main reasons we moved to copper. It allows for greatly increased packing density due to combination of better electrical characteristics at high aspect ratios and reduced electromigration effects.
Well since an announcement of such a major purchase would typically cause a significant drop in AAPL shares, it might explain the top executive's sell off of Apple stock. Also the news of 1 GHz upgrades being available in the aftermarket might be a result of Moto dumping existing stocks of G4's into that market.</strong><hr></blockquote>
Well considering all of recent poor corporate pr on insider trading and numbers fudging, if these Apple execs did act on insider info, they better start raising cash for legal fees now.
Comments
<strong>
Well if the "wires" all ran in one direction that would be true, but they actually run in 2 (and a half - multiple layers), so a thinner wire makes for closer wires in all dimensions that you are using.</strong><hr></blockquote>
While that is true remember that as mmcist pointed out a processor is limited by the speed of its transistors and the speed of its interconnects. Transistors are sped up by decreasing channel lengths, channel widths (the other dimension) are usually kept the same in order to provide increased current drive. The wider your pipe is the more current you can flow through it and force your capacitive transistors to transition.
Interconnects are similar, you want a low resistance path for your signals to travel. Therefore you want your metal lines to be as wide as possible while decreasing the length. Thus while you can increase your packing density by decreasing interconnect width it is a tradeoff with your electrical characteristics. Also as you increase the packing density of your metal lines by putting them closer together you increase the relative capacitance between the lines which also slows down your part. Capacitance is defined as being equal to k*A/t where k is your dielectric constant, A the area, and t your thickness. The spacing between metal lines can be viewed as t. So in order to counteract packing interconnects closer together you often look to lower your k value at the same time. This is the reason for all the research into low k dielectric materials currently in the semiconductor industry.
[ 07-02-2002: Message edited by: Shanny ]</p>
<strong>
While that is true remember that as mmcist pointed out a processor is limited by the speed of its transistors and the speed of its interconnects. Transistors are sped up by decreasing channel lengths, channel widths (the other dimension) are usually kept the same in order to provide increased current drive. The wider your pipe is the more current you can flow through it and force your capacitive transistors to transition.
Interconnects are similar, you want a low resistance path for your signals to travel. Therefore you want your metal lines to be as wide as possible while decreasing the length. Thus while you can increase your packing density by decreasing interconnect width it is a tradeoff with your electrical characteristics. Also as you increase the packing density of your metal lines by putting them closer together you increase the relative capacitance between the lines which also slows down your part. Capacitance is defined as being equal to k*A/t where k is your dielectric constant, A the area, and t your thickness. The spacing between metal lines can be viewed as t. So in order to counteract packing interconnects closer together you often look to lower your k value at the same time. This is the reason for all the research into low k dielectric materials currently in the semiconductor industry.</strong><hr></blockquote>
Yes, a slightly fuller explanation than mine. Although I would add that as well as resistance limiting the dimensions of interconnects, electromigration limits how close interconnects can be to each other (especially at corners), this is a serious problem in current processes.
Michael
<strong>
Yes, a slightly fuller explanation than mine. Although I would add that as well as resistance limiting the dimensions of interconnects, electromigration limits how close interconnects can be to each other (especially at corners), this is a serious problem in current processes.
Michael</strong><hr></blockquote>
Which is one of the main reasons we moved to copper. It allows for greatly increased packing density due to combination of better electrical characteristics at high aspect ratios and reduced electromigration effects.
<strong>
Well since an announcement of such a major purchase would typically cause a significant drop in AAPL shares, it might explain the top executive's sell off of Apple stock. Also the news of 1 GHz upgrades being available in the aftermarket might be a result of Moto dumping existing stocks of G4's into that market.</strong><hr></blockquote>
Well considering all of recent poor corporate pr on insider trading and numbers fudging, if these Apple execs did act on insider info, they better start raising cash for legal fees now.