Yes the two FPUs would be able to do 2x64 bit SIMD instructions, but this would be an extension to AltiVec, and would'nt be any faster than using standard FPU instructions except in rare cases, so I can't see any developer bothering.</strong>
I can agree with, I also agree with you that a indepent SIMD unit or units are the best way to go, but my thoughts are more about marketing and money than engineering. Since Intel SSE2 does it, why not have this GPUL do it. If I was Apple, the thought would cross my mind. And if it was truly a pipelined operation, it should be just as fast or faster at half the clock rate of a prospective P4.
<strong>Unfortunately using the FPUs to do the 4x32bit FP SIMD instructions would slow things down by a factor of 2.</strong>
Why would this be so? IBM has previously, and presumably managed by the same person, Peter Sandon, as well, split the PPC 750 FPU to do 2x32 SIMD instructions for the Gekko, given that the Gekko SIMD is very limited. It is something the IBM team has experience in.
<strong>As far as integer instructions are concerned, you could mostly do it with modified integer units, but not the permute instructions. The masking elements of the instructions would almost certainly slow down implementations using the scalar execution units.</strong>
Yes, the permute instructions would be a problem. Either the integer units have to be modified to do permutes or a new unit has to be put in.
<strong>It has so many advantages its difficult to list them all, but why go to all the bother of redesigning them to be able to execute SIMD instructions, (they would need new ports to the SIMD registers at a very minimum, and probably a fair bit more) when it would be reasonably simple to add on a proper SIMD unit, given you have to add the registers and at least a permute unit, giving greater chances for instruction parallelism and improved performance, at the cost of a few million transistors.</strong>
I'm not sure. My premise is that if using the FP and integer units provide a 90% solution for less cost, then I can see them doing it. Now whether modifying the current units to do SIMD instructions is cheaper than adding a new execution unit, or vice versa, is an interesting question I'm not qualified to explore.
A Altivec Unit sharing ressources with the FP and integer unit will save many transistors, but will require a nearly entirely new design of the core at the contrary to the Gekko design who was a limited SIMD unit.
It will be difficult for IBM engineers to predict how will work this new design when switching from Altivec mode to FPU or integer mode. At the contrary they have a huge experience of how react their a classical core whether it's a 32 bit or 64 bit one, thus adding a separated Altivc unit will aloud the enginneers to benefit of the work and experience of their previous design.
In resume : shared units means a save of transistors, but less performance and more R&D. And of course i am not qualified to bring an answer, but like everybody here i expect that the altivec unit will be a good one, because the VE is the only amazing technology in a G4.
What's the latency in switching from SIMD mode to normal mode and vice versa? If one cycle then that is not too bad. If more than 4 then you may see some degraded performance.
Also if this is a dual core processor you can still reap the benefits of dual processors while using non SIMD code then when SIMD code is being executed alongside normal code, only one core reverts to SIMD mode.
I'm not sure. My premise is that if using the FP and integer units provide a 90% solution for less cost, then I can see them doing it. Now whether modifying the current units to do SIMD instructions is cheaper than adding a new execution unit, or vice versa, is an interesting question I'm not qualified to explore.</strong><hr></blockquote>
My belief is that any such modification to the core would probably be more expensive than the addition of a separate SIMD unit, as it would involve the redesign of the existing units to enable them to do more than one thing. This would undoubtedly also introduce new bugs, need more testing, and crucially require new work every time the core was updated. If you use a largely unmodified POWER4 core, with separate SIMD unit, then every time the POWER4 core is updated the new core can be slipped into the new GPUL, if you have to redesign the functional units for the GPUL, that will mean significant new cost for every iteration.
I see no reason to save a very small amount on the die cost, at the expense of a replacing first class implementation with a poorer one, and ongoing development costs.
My belief is that any such modification to the core would probably be more expensive than the addition of a separate SIMD unit, as it would involve the redesign of the existing units to enable them to do more than one thing. This would undoubtedly also introduce new bugs, need more testing, and crucially require new work every time the core was updated. If you use a largely unmodified POWER4 core, with separate SIMD unit, then every time the POWER4 core is updated the new core can be slipped into the new GPUL, if you have to redesign the functional units for the GPUL, that will mean significant new cost for every iteration.
I see no reason to save a very small amount on the die cost, at the expense of a replacing first class implementation with a poorer one, and ongoing development costs.
I'll note that a person over in the Arstechnica forums supposedly saw a floor plan for the GPUL quite awhile ago, and from what is described, the GPUL SIMD unit (VMX unit) is a separate unit. Said floor plan was to be redone, but if this info is true, than the GPUL has a separate unit. Now hopefully, this unit will be fully pipelined.
Comments
Yes the two FPUs would be able to do 2x64 bit SIMD instructions, but this would be an extension to AltiVec, and would'nt be any faster than using standard FPU instructions except in rare cases, so I can't see any developer bothering.</strong>
I can agree with, I also agree with you that a indepent SIMD unit or units are the best way to go, but my thoughts are more about marketing and money than engineering. Since Intel SSE2 does it, why not have this GPUL do it. If I was Apple, the thought would cross my mind. And if it was truly a pipelined operation, it should be just as fast or faster at half the clock rate of a prospective P4.
<strong>Unfortunately using the FPUs to do the 4x32bit FP SIMD instructions would slow things down by a factor of 2.</strong>
Why would this be so? IBM has previously, and presumably managed by the same person, Peter Sandon, as well, split the PPC 750 FPU to do 2x32 SIMD instructions for the Gekko, given that the Gekko SIMD is very limited. It is something the IBM team has experience in.
<strong>As far as integer instructions are concerned, you could mostly do it with modified integer units, but not the permute instructions. The masking elements of the instructions would almost certainly slow down implementations using the scalar execution units.</strong>
Yes, the permute instructions would be a problem. Either the integer units have to be modified to do permutes or a new unit has to be put in.
<strong>It has so many advantages its difficult to list them all, but why go to all the bother of redesigning them to be able to execute SIMD instructions, (they would need new ports to the SIMD registers at a very minimum, and probably a fair bit more) when it would be reasonably simple to add on a proper SIMD unit, given you have to add the registers and at least a permute unit, giving greater chances for instruction parallelism and improved performance, at the cost of a few million transistors.</strong>
I'm not sure. My premise is that if using the FP and integer units provide a 90% solution for less cost, then I can see them doing it. Now whether modifying the current units to do SIMD instructions is cheaper than adding a new execution unit, or vice versa, is an interesting question I'm not qualified to explore.
It will be difficult for IBM engineers to predict how will work this new design when switching from Altivec mode to FPU or integer mode. At the contrary they have a huge experience of how react their a classical core whether it's a 32 bit or 64 bit one, thus adding a separated Altivc unit will aloud the enginneers to benefit of the work and experience of their previous design.
In resume : shared units means a save of transistors, but less performance and more R&D. And of course i am not qualified to bring an answer, but like everybody here i expect that the altivec unit will be a good one, because the VE is the only amazing technology in a G4.
Also if this is a dual core processor you can still reap the benefits of dual processors while using non SIMD code then when SIMD code is being executed alongside normal code, only one core reverts to SIMD mode.
<strong>
I'm not sure. My premise is that if using the FP and integer units provide a 90% solution for less cost, then I can see them doing it. Now whether modifying the current units to do SIMD instructions is cheaper than adding a new execution unit, or vice versa, is an interesting question I'm not qualified to explore.</strong><hr></blockquote>
My belief is that any such modification to the core would probably be more expensive than the addition of a separate SIMD unit, as it would involve the redesign of the existing units to enable them to do more than one thing. This would undoubtedly also introduce new bugs, need more testing, and crucially require new work every time the core was updated. If you use a largely unmodified POWER4 core, with separate SIMD unit, then every time the POWER4 core is updated the new core can be slipped into the new GPUL, if you have to redesign the functional units for the GPUL, that will mean significant new cost for every iteration.
I see no reason to save a very small amount on the die cost, at the expense of a replacing first class implementation with a poorer one, and ongoing development costs.
michael
<strong>
My belief is that any such modification to the core would probably be more expensive than the addition of a separate SIMD unit, as it would involve the redesign of the existing units to enable them to do more than one thing. This would undoubtedly also introduce new bugs, need more testing, and crucially require new work every time the core was updated. If you use a largely unmodified POWER4 core, with separate SIMD unit, then every time the POWER4 core is updated the new core can be slipped into the new GPUL, if you have to redesign the functional units for the GPUL, that will mean significant new cost for every iteration.
I see no reason to save a very small amount on the die cost, at the expense of a replacing first class implementation with a poorer one, and ongoing development costs.
michael</strong><hr></blockquote>
yes it's also my very humble opinion.