<strong>If ST buys Motorola's semiconductor division (including PowerPC) then there might actually be some improvements. Certainly it can't be any worse than staying under Motorola ownership! ST may have enough strength and backbone to want to compete with Intel in the desktop processor market.</strong><hr></blockquote>
But would they do it with a PPC or anything compatible with a PPC ??? And would M$ want to throw support to such a chip knowiing that a very good competing platform exists on it? I dunno, what are the possibilities?
But would they do it with a PPC or anything compatible with a PPC ??? And would M$ want to throw support to such a chip knowiing that a very good competing platform exists on it? I dunno, what are the possibilities?</strong><hr></blockquote>
Well, for a while when the PPC was intro'd and Apple was still an almost viable competitor with MS, MS had NT running on and available for PPC.
Can you really believe this document from Motorola. They've fallen flat on every promise on this roadmap since the G4 was introduced, and it's pretty clear that the company wants to sell this division.
This is nothing but marketing bumf. There are no promised dates or features, just vague graphs that point to more features and performance in the future.
Heck, when this presentation was made in July of this year, they were suggesting a .10 µ process by year end 2002 (slide 16). I bet you we don't get it.
"Error No. 10: Altivec lvxl/stvxl instructions allocate lines in the L2/L3
caches
Overview:
The lvxl/stvxl Altivec instructions are defined to be transient and not allocate into the L2/L3
caches. However, allocation does occur for these instructions.
Detailed Description:
On the MPC7450, a typical cacheable load-type instruction allocates data simultaneously in the L1
data cache (dL1), L2, and L3 caches. In the dL1, the line is allocated in the most-recently-used
state. If the line is deallocated from the dL1, then the data may still reside in the L2 or L3, thus
preventing an access to main memory.
This method works efficiently for addresses that are frequently accessed, but is inefficient for
addresses that are utilized just once.
For the latter type of addresses, the Altivec architecture defines the lvxl and stvxl instructions that
leave dL1 cache entries in least-recently-used state instead of most-recently-used state. In addition,
for the MPC74xx and MPC75xx family of parts, these load-type operations are defined as
transient, and therefore, should not allocate data in the L2 (and L3) cache(s). As a result, addresses
that are accessed just once will not occupy valuable L2 (or L3) cache real estate.
For the lvxl/stvxl instructions, the MPC7450 correctly implements the least-recently-used feature
in the dL1, but does not implement the transient behavior for the L2 and L3."
(emphasis added)
So it would appear that at least internally, there is a 75xx family of processors kicking around at Motorola. Maybe these are the fabled "G5s" of yore. Maybe they'll see the light of day yet. Maybe there really is a Santa Claus.
A few key things of interest I got from about my third careful reading of the Motorola PDF (which had a Sept. 23, 2002 creation date):
Apollo is the name of the next chip and while based on 7450 it is a new and different architechture.
Based on the timeline (extrapolated to the dates the 7450/ 0.18 process shipped in Apple boxes), we could indeed see Apollo in Apple boxes in the first calendar Q of 2003.
Apollo will produce 8 watts running at 1 GHz which is apparently its imbedded speed/power target. I think we're looking at significantly more, like 1.5 GHz at least, as a desktop CPU consuming twice the wattage.
Apollo will be "software compatible with G3 & G4" which possibly indicates it will be an entirely new beast... (dare I say it?)... a G5 !
Is it just me or has 'Apollo' (the code name for the 7450) been out for over a year? The 7455 is the 'Apollo6' and i think what you may be referring to is the 'Apollo7' (a 130nm G4).
Is it just me or has 'Apollo' (the code name for the 7450) been out for over a year? The 7455 is the 'Apollo6' and i think what you may be referring to is the 'Apollo7' (a 130nm G4).
</strong>
The original Apollo description from MPF00 was of a 0.13 micron product. If one is cynical, and it seems apt for Moto, Moto has been having huge troubles with the HiP 7 ramp up, and remarketed "Apollo" as a 0.18u SOI product instead of a 0.13u SOI product.
Apple really really needs a 0.13 micron G4. It would be great for iBooks, eMacs, iMacs and Powerbooks.
I know of a MPC 7457 from Motorola witch will be sampling shortly on 130 nm process at 867-1833 MHz. It will ship early next year with it's larger brother, 7457-RM, comming perhaps in 2004 witch RapidIO-powered DDR-SDRAM at 1.3-2.0+ GHz.
They arent adopting DDR or Rapid IO till 2004. The only thing that I see encouraging about this is that Moto will have a viable G4/5 style chip for Apples consumer line-up through the end of 2004, though its speeds will still be lagging behind the Intel offerings.
Still Apple does have the IBM chip to help out in the pro lin-up...but up untill then Apple is going to have a hard time competing in the high end market.
Steve needs something to pull out of his hat soon for his stock holders, and the continued stability of the Mac platform. OS X should be bringing a lot more swithchers in the high end arena, but the lackluster hardware that Apple has been able to produce since its introduction has really hurt Apple's ability to sell to these markets.
<strong>What can we expact in January?</strong><hr></blockquote>We can expect 750FX reaching 1.2 GHz in its Polaris strain in 2003. But I don't expect to see those in Macs for a while..
Well since the 750 is a G3, the only Mac this could be put in is the iBook. I find it hard to believe that Apple will have a faster clocked iBook than Powerbook.
Comments
<strong>If ST buys Motorola's semiconductor division (including PowerPC) then there might actually be some improvements. Certainly it can't be any worse than staying under Motorola ownership! ST may have enough strength and backbone to want to compete with Intel in the desktop processor market.</strong><hr></blockquote>
But would they do it with a PPC or anything compatible with a PPC ??? And would M$ want to throw support to such a chip knowiing that a very good competing platform exists on it? I dunno, what are the possibilities?
<strong>
But would they do it with a PPC or anything compatible with a PPC ??? And would M$ want to throw support to such a chip knowiing that a very good competing platform exists on it? I dunno, what are the possibilities?</strong><hr></blockquote>
Well, for a while when the PPC was intro'd and Apple was still an almost viable competitor with MS, MS had NT running on and available for PPC.
This is nothing but marketing bumf. There are no promised dates or features, just vague graphs that point to more features and performance in the future.
Heck, when this presentation was made in July of this year, they were suggesting a .10 µ process by year end 2002 (slide 16). I bet you we don't get it.
<a href="http://e-www.motorola.com/brdata/PDFDB/docs/MPC7450CE.pdf"; target="_blank">MPC7450 family errata (PDF)</a>
"Error No. 50: Altivec lvxl/stvxl instructions allocate lines in the L2/L3
caches
Overview:
The lvxl/stvxl Altivec instructions are defined to be transient and not allocate into the L2/L3
caches. However, allocation does occur for these instructions.
Detailed Description:
On the MPC7450, a typical cacheable load-type instruction allocates data simultaneously in the L1
data cache (dL1), L2, and L3 caches. In the dL1, the line is allocated in the most-recently-used
state. If the line is deallocated from the dL1, then the data may still reside in the L2 or L3, thus
preventing an access to main memory.
This method works efficiently for addresses that are frequently accessed, but is inefficient for
addresses that are utilized just once.
For the latter type of addresses, the Altivec architecture defines the lvxl and stvxl instructions that
leave dL1 cache entries in least-recently-used state instead of most-recently-used state. In addition,
for the MPC74xx and MPC75xx family of parts, these load-type operations are defined as
transient, and therefore, should not allocate data in the L2 (and L3) cache(s). As a result, addresses
that are accessed just once will not occupy valuable L2 (or L3) cache real estate."
(emphasis added)
and from
<a href="http://e-www.motorola.com/brdata/PDFDB/docs/MPC7455CE.pdf"; target="_blank">MPC7455 Errata</a>
"Error No. 10: Altivec lvxl/stvxl instructions allocate lines in the L2/L3
caches
Overview:
The lvxl/stvxl Altivec instructions are defined to be transient and not allocate into the L2/L3
caches. However, allocation does occur for these instructions.
Detailed Description:
On the MPC7450, a typical cacheable load-type instruction allocates data simultaneously in the L1
data cache (dL1), L2, and L3 caches. In the dL1, the line is allocated in the most-recently-used
state. If the line is deallocated from the dL1, then the data may still reside in the L2 or L3, thus
preventing an access to main memory.
This method works efficiently for addresses that are frequently accessed, but is inefficient for
addresses that are utilized just once.
For the latter type of addresses, the Altivec architecture defines the lvxl and stvxl instructions that
leave dL1 cache entries in least-recently-used state instead of most-recently-used state. In addition,
for the MPC74xx and MPC75xx family of parts, these load-type operations are defined as
transient, and therefore, should not allocate data in the L2 (and L3) cache(s). As a result, addresses
that are accessed just once will not occupy valuable L2 (or L3) cache real estate.
For the lvxl/stvxl instructions, the MPC7450 correctly implements the least-recently-used feature
in the dL1, but does not implement the transient behavior for the L2 and L3."
(emphasis added)
So it would appear that at least internally, there is a 75xx family of processors kicking around at Motorola. Maybe these are the fabled "G5s" of yore. Maybe they'll see the light of day yet. Maybe there really is a Santa Claus.
Apollo is the name of the next chip and while based on 7450 it is a new and different architechture.
Based on the timeline (extrapolated to the dates the 7450/ 0.18 process shipped in Apple boxes), we could indeed see Apollo in Apple boxes in the first calendar Q of 2003.
Apollo will produce 8 watts running at 1 GHz which is apparently its imbedded speed/power target. I think we're looking at significantly more, like 1.5 GHz at least, as a desktop CPU consuming twice the wattage.
Apollo will be "software compatible with G3 & G4" which possibly indicates it will be an entirely new beast... (dare I say it?)... a G5 !
At least I didn't say "CONFIRMED"
[ 10-18-2002: Message edited by: Outsider ]</p>
Is it just me or has 'Apollo' (the code name for the 7450) been out for over a year? The 7455 is the 'Apollo6' and i think what you may be referring to is the 'Apollo7' (a 130nm G4).
</strong>
The original Apollo description from MPF00 was of a 0.13 micron product. If one is cynical, and it seems apt for Moto, Moto has been having huge troubles with the HiP 7 ramp up, and remarketed "Apollo" as a 0.18u SOI product instead of a 0.13u SOI product.
Apple really really needs a 0.13 micron G4. It would be great for iBooks, eMacs, iMacs and Powerbooks.
.13 G4 ('G5')? A 7500 'Super G4'..?
We'll see.
Only just over 2 months to go anyhow to the next Macworld.
Lemon Bon Bon
<a href="http://e-www.motorola.com/collateral/SNDF2002RECAP_Q1228.pdf"; target="_blank">http://e-www.motorola.com/collateral/SNDF2002RECAP_Q1228.pdf</a>;
Nice! Beats the 970 in terms of raw MHz and is slated for early 2003? Now now, Motorola, why have you been holding out on us?
Still Apple does have the IBM chip to help out in the pro lin-up...but up untill then Apple is going to have a hard time competing in the high end market.
Steve needs something to pull out of his hat soon for his stock holders, and the continued stability of the Mac platform. OS X should be bringing a lot more swithchers in the high end arena, but the lackluster hardware that Apple has been able to produce since its introduction has really hurt Apple's ability to sell to these markets.
<strong>That one was easy, yet cool.. I have more cool stuff from IBM too.. Interessted?</strong><hr></blockquote>
common give it to me, rumor machine ;-) ...
[ 10-18-2002: Message edited by: Bigc ]</p>
<strong>That one was easy, yet cool.. I have more cool stuff from IBM too.. Interessted?</strong><hr></blockquote>
YEAH!
What can we expact in January <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
<strong>What can we expact in January?</strong><hr></blockquote>We can expect 750FX reaching 1.2 GHz in its Polaris strain in 2003. But I don't expect to see those in Macs for a while..
[ 10-18-2002: Message edited by: Henriok ]</p>
<strong>We can expect 750FX reaching 1.2 GHz in its Polaris strain in 2003. But I don't expect to see those in Macs for a while..
[ 10-18-2002: Message edited by: Henriok ]</strong><hr></blockquote>
Well since the 750 is a G3, the only Mac this could be put in is the iBook. I find it hard to believe that Apple will have a faster clocked iBook than Powerbook.