DDR-II ? Even then doesn't it maxx out around 4.2GB/s. Maybe some kinda dual channel interleaved DDR-II solution?
Any answers?</strong><hr></blockquote>
Yea... I forgot didn't they call a stop to all advances in memory technology? Sorry for the dig but it was aching to be said.
Fact is I'd rather have a CPU that support more than what TODAYS memory can do since as we all know nothing stands still. Heck we are going from a cpu that maxes out at 166Mhz to a cpu that maxes out at 900Mhz this IS a GOOD THING(tm) trust me!
Again I didn't mean to take that swipe but all we need are folks going around using THAT as a reason to think the CPU is sub-standard.
I didn't mean it as a criticism, I was honestly wondering what the next step will be? Absolutely better to have a higher FSB limit than a lower one, I don't see how anyone could use it as a knock against the CPU.
<strong>1.8 GHz, relatively low power consumption, a likely quick move to 0.09 microns, 6.4 GB/sec memory bandwidth, a full VMX implementation, full speed 32-bit mode, 64-bit support, 8/5-way superscalar, ~1000 int & fp specmarks, 96K L1 cache, 512K L2 cache, full SMP support up to 16-way (!!), all packed into only ~50 million transistors and you guys are still complaining??</strong><hr></blockquote>
<strong>I didn't mean it as a criticism, I was honestly wondering what the next step will be? Absolutely better to have a higher FSB limit than a lower one, I don't see how anyone could use it as a knock against the CPU.</strong><hr></blockquote>
The next step is DDR II, but that's not what the 6.4GB/s of bandwidth is really for.
Think Apple Processor Interconnect. There are a number of ways Apple could lay this out, but imagine communication between processors at that speed! Heck, Apple could fit RAM and AGP bandwidth on one bus and have room to grow.
This is workstation grade stuff. This is very cool. And it's the kind of thing that SPEC doesn't even touch.
Speaking of things SPEC doesn't touch, you know that one little thing that allows a G4 to completely smoke a P4? AltiVec? Well, this chip's got it on board too. How badly will it smoke the competition once that's taken into account? Keep in mind that there is currently more than one effort to optimize PPC Linux for AltiVec. Apple is not alone here. Can you imagine what top-flight SPEC marks, unheard-of (for PCs) bandwidth, unheard-of (for PCs) MP capabilities, full-blown AltiVec, all crammed into a small, cool processor is going to do? Especially since the GPU will be conscripted to take a lot of the work away from them in OS X?
Even if something bests it by 10% or so in SPEC marks by the time it comes out, it'll still own in overall, real-world power and in power/initial cost and, because it's relatively small and cool, in power/watt. And it'll be in PowerBooks! If not immediately, then before long.
Oh, and it won't introduce a whole new ISA (like Itanic) nor (apparently) require hard resets to go from 32 to 64 bit mode (like Opteron).
This is the best goddamn news to hit the PowerPC world since... I don't know, the PowerPC. And, astonishingly, people are still whining. Get a grip, people. This rocks. IBM surpassed my expectations by a comfortable margin: I expected something like this level of performance, but I thought the tradeoff would be a big, hot, expensive monster. Not something that could ship in a notebook right off the bat!
[quote]The IBM CPU will also give us things we've never had:
- 64 Bit computing - Unlike the P4<hr></blockquote>
here's something i need some explaining on
We've got a 970
can you mix and match 64-bit/32-bit apps on a 64-bit OSX?
Can you mix and match 64/32 on a 32-bit OSX?
Wouldn't everything have to be the same all across?
and also, would performance be different running 32bit apps/OS compared to 64bit apps/os?
I've read previously that 64bit apps/os would be slightly slower in some respects because of larger chunks goin through, wasting a bit more space here and there.
Can we mix and match this stuff?
If not - then the GPUL970IBMthingamajib won't give us 64-bit
Apple and software developers will have to.
And a reminder - what exactly needs to be done for 32but apps to go 64bit?
Just a recompile?
Or recompile and tweaking?
(meaning, software companies would wait until a larger .5 or .0 release to implement it)
regardless - this is kinda exciting.
although I thought the IBMGPUL970thingamajib would end up wiping the floor with the Itantium 2 - but hey - the Itantium 2 needs 64-bit windows and apps. WinXP-64 is out - a lot of apps aint.
(not to mention the cost!)
Carry on.
(and can one of the admins puh-leeeease fix that ridiculously long URL above? It's ruining my enjoyment of this page! Thanks.)
GPUL's VMX == AltiVec, this is confirmed. It has 2 VMX units.
Don't worry about 32-bit vs 64-bit compatibility, the OS that runs on these machines will run both kinds of software natively and at full speed. If you don't have any word-size assumptions in your code then you can just recompile into 64-bit mode, but why would you unless you are taking advantage of the 64-bitness of it? Otherwise just recompile the 32-bit app with a GPUL-aware compiler and there will likely be a bit of a performance improvement.
IBM will use a 0.13-micron SOI process with 8 levels of copper to manufacture the chip, which should require a 576 pin package; Sandon did not disclose the die size. IBM expects the chip will output between 19 watts and 42 watts of power, depending on the whether a 1.2-GHz (1.1 volts operating voltage) or 1.8-GHz (1.3 volt) clock speed is used.
It'll be moving to .09 micron relatively quickly, too, which means that if Apple can't get it in a PowerBook (or an iMac!) right off the bat they'll be able to before long.
Given this spec, the 667, which I believe is the one in the PBG4 667, uses 19watts.
In an ideal world I'd like the 970 to completely scrap the compatibility factor and lose a couple-million transistors in the process, but I'll take what I can get.
So, while I don't guess that Apple will immediately launch a bad-ass PB970, it looks as though it may be an option. Secondly, I don't know how much is to gain by reducing the fab size. How much lower can the voltage go before it's below the threshold for Si? I think the bottom limit > 0.7V.
. . . So if 90nm can move to 1V, or maybe even 0.9V I guess that will help a bit.
This is a far more telling quote from the same article:
[quote]
Perhaps more importantly, the front-side bus can transfer up to 7.2 Gbytes per second, roughly four times the bandwidth of the current Pentium 4 front-side bus, according to MDR's Halfhill.
<hr></blockquote>
I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.
<strong>In an ideal world I'd like the 970 to completely scrap the compatibility factor and lose a couple-million transistors in the process, but I'll take what I can get.
</strong><hr></blockquote>
Which "compatibility factor" are you refering to?!
[quote]<strong>
So, while I don't guess that Apple will immediately launch a bad-ass PB970, it looks as though it may be an option. Secondly, I don't know how much is to gain by reducing the fab size. How much lower can the voltage go before it's below the threshold for Si? I think the bottom limit > 0.7V.
. . . So if 90nm can move to 1V, or maybe even 0.9V I guess that will help a bit.
</strong><hr></blockquote>
I don't know about the voltage reduction, but the smaller process means a smaller die. A smaller die means more parts per wafer which means better yields and thus cheaper parts. It should also allow higher clock rates.
Really? 2 subunits like the 7400 (VPU + VALU) or two full units or how do I have to understand this? Where can I read about it?
G4@1GHz: 10.5M RC5 keys/s
GPUL@1.8GHz: 18M RC5 keys/s
Hmm... ok.</strong><hr></blockquote>
Linear scaling by clock rate isn't surprising. In fact, its a relief. I was concerned that we'd lose some of AltiVec's magic efficiency with the introduction of IBM's VMX equivalent. RC5 isn't very bandwidth intensive, I believe, so you're not seeing the benefits of the 6.4x improvement in bandwidth.
Comments
<strong>What kinda RAM is gonna feed that FSB ???
DDR-II ? Even then doesn't it maxx out around 4.2GB/s. Maybe some kinda dual channel interleaved DDR-II solution?
Any answers?</strong><hr></blockquote>
Yea... I forgot didn't they call a stop to all advances in memory technology? Sorry for the dig but it was aching to be said.
Fact is I'd rather have a CPU that support more than what TODAYS memory can do since as we all know nothing stands still. Heck we are going from a cpu that maxes out at 166Mhz to a cpu that maxes out at 900Mhz this IS a GOOD THING(tm) trust me!
Again I didn't mean to take that swipe but all we need are folks going around using THAT as a reason to think the CPU is sub-standard.
Dave
[ 10-15-2002: Message edited by: DaveGee ]</p>
Read through the old posts--actually, at 1.2 gig it only uses 19 WATTS (emphasis mine).
I can smell portables showing up a hell of a lot sooner!
<strong>1.8 GHz, relatively low power consumption, a likely quick move to 0.09 microns, 6.4 GB/sec memory bandwidth, a full VMX implementation, full speed 32-bit mode, 64-bit support, 8/5-way superscalar, ~1000 int & fp specmarks, 96K L1 cache, 512K L2 cache, full SMP support up to 16-way (!!), all packed into only ~50 million transistors and you guys are still complaining??</strong><hr></blockquote>
I couldn't agree more.
[ 10-15-2002: Message edited by: Ensign Pulver ]</p>
<strong>I didn't mean it as a criticism, I was honestly wondering what the next step will be? Absolutely better to have a higher FSB limit than a lower one, I don't see how anyone could use it as a knock against the CPU.</strong><hr></blockquote>
The next step is DDR II, but that's not what the 6.4GB/s of bandwidth is really for.
Think Apple Processor Interconnect. There are a number of ways Apple could lay this out, but imagine communication between processors at that speed! Heck, Apple could fit RAM and AGP bandwidth on one bus and have room to grow.
This is workstation grade stuff. This is very cool. And it's the kind of thing that SPEC doesn't even touch.
Speaking of things SPEC doesn't touch, you know that one little thing that allows a G4 to completely smoke a P4? AltiVec? Well, this chip's got it on board too. How badly will it smoke the competition once that's taken into account? Keep in mind that there is currently more than one effort to optimize PPC Linux for AltiVec. Apple is not alone here. Can you imagine what top-flight SPEC marks, unheard-of (for PCs) bandwidth, unheard-of (for PCs) MP capabilities, full-blown AltiVec, all crammed into a small, cool processor is going to do? Especially since the GPU will be conscripted to take a lot of the work away from them in OS X?
Even if something bests it by 10% or so in SPEC marks by the time it comes out, it'll still own in overall, real-world power and in power/initial cost and, because it's relatively small and cool, in power/watt. And it'll be in PowerBooks! If not immediately, then before long.
Oh, and it won't introduce a whole new ISA (like Itanic) nor (apparently) require hard resets to go from 32 to 64 bit mode (like Opteron).
This is the best goddamn news to hit the PowerPC world since... I don't know, the PowerPC. And, astonishingly, people are still whining. Get a grip, people. This rocks. IBM surpassed my expectations by a comfortable margin: I expected something like this level of performance, but I thought the tradeoff would be a big, hot, expensive monster. Not something that could ship in a notebook right off the bat!
[ 10-15-2002: Message edited by: Amorph ]
[ 10-15-2002: Message edited by: Amorph ]</p>
-G
- 64 Bit computing - Unlike the P4<hr></blockquote>
here's something i need some explaining on
We've got a 970
can you mix and match 64-bit/32-bit apps on a 64-bit OSX?
Can you mix and match 64/32 on a 32-bit OSX?
Wouldn't everything have to be the same all across?
and also, would performance be different running 32bit apps/OS compared to 64bit apps/os?
I've read previously that 64bit apps/os would be slightly slower in some respects because of larger chunks goin through, wasting a bit more space here and there.
Can we mix and match this stuff?
If not - then the GPUL970IBMthingamajib won't give us 64-bit
Apple and software developers will have to.
And a reminder - what exactly needs to be done for 32but apps to go 64bit?
Just a recompile?
Or recompile and tweaking?
(meaning, software companies would wait until a larger .5 or .0 release to implement it)
regardless - this is kinda exciting.
although I thought the IBMGPUL970thingamajib would end up wiping the floor with the Itantium 2 - but hey - the Itantium 2 needs 64-bit windows and apps. WinXP-64 is out - a lot of apps aint.
(not to mention the cost!)
Carry on.
(and can one of the admins puh-leeeease fix that ridiculously long URL above? It's ruining my enjoyment of this page! Thanks.)
[ 10-15-2002: Message edited by: cinder ]</p>
Don't worry about 32-bit vs 64-bit compatibility, the OS that runs on these machines will run both kinds of software natively and at full speed. If you don't have any word-size assumptions in your code then you can just recompile into 64-bit mode, but why would you unless you are taking advantage of the 64-bitness of it? Otherwise just recompile the 32-bit app with a GPUL-aware compiler and there will likely be a bit of a performance improvement.
19 watts @ 1.2 GHz! WOW!
[ 10-15-2002: Message edited by: Programmer ]</p>
I want a 64bit notebook, I just want it, Apple, you might finally earn a sale, imagine that...
I could be in a switch add, an anti-switch add of sorts,
"You know, it's fvcking fast! Forget all the other bullsiht, it's fast." Do do do... Apple music playing in background... "BTW, it's fast!"
"My name is Matsu, and I used to dream of burning Cupertino to the ground..."
from <a href="http://www.extremetech.com/article2/0,3973,635220,00.asp"; target="_blank">http://www.extremetech.com/</a>;
edit: whoops, redundant. sorry.
[ 10-15-2002: Message edited by: cinder ]</p>
<strong>
It'll be moving to .09 micron relatively quickly, too, which means that if Apple can't get it in a PowerBook (or an iMac!) right off the bat they'll be able to before long.
</strong><hr></blockquote>
<a href="http://www.geek.com/procspec/apple/g4.htm"; target="_blank">http://www.geek.com/procspec/apple/g4.htm</a>;
Given this spec, the 667, which I believe is the one in the PBG4 667, uses 19watts.
In an ideal world I'd like the 970 to completely scrap the compatibility factor and lose a couple-million transistors in the process, but I'll take what I can get.
So, while I don't guess that Apple will immediately launch a bad-ass PB970, it looks as though it may be an option. Secondly, I don't know how much is to gain by reducing the fab size. How much lower can the voltage go before it's below the threshold for Si? I think the bottom limit > 0.7V.
. . . So if 90nm can move to 1V, or maybe even 0.9V I guess that will help a bit.
This time around it better be andonized. . .
[ 10-15-2002: Message edited by: Splinemodel ]</p>
<strong>GPUL's VMX == AltiVec, this is confirmed. It has 2 VMX units.</strong><hr></blockquote>
Really? 2 subunits like the 7400 (VPU + VALU) or two full units or how do I have to understand this? Where can I read about it?
G4@1GHz: 10.5M RC5 keys/s
GPUL@1.8GHz: 18M RC5 keys/s
Hmm... ok.
[quote]
Perhaps more importantly, the front-side bus can transfer up to 7.2 Gbytes per second, roughly four times the bandwidth of the current Pentium 4 front-side bus, according to MDR's Halfhill.
<hr></blockquote>
I don't know where he gets 7.2, but even at 6.4 that means it'll be doing considerably better than the PIV's FSB... and then consider that in most applications AltiVec is currently held back almost entirely by memory bandwidth. If Apple builds a top-of-the-line memory system to feed this beast I think we're going to see some very impressive media performance -- something that SPEC doesn't even attempt to benchmark.
<strong>In an ideal world I'd like the 970 to completely scrap the compatibility factor and lose a couple-million transistors in the process, but I'll take what I can get.
</strong><hr></blockquote>
Which "compatibility factor" are you refering to?!
[quote]<strong>
So, while I don't guess that Apple will immediately launch a bad-ass PB970, it looks as though it may be an option. Secondly, I don't know how much is to gain by reducing the fab size. How much lower can the voltage go before it's below the threshold for Si? I think the bottom limit > 0.7V.
. . . So if 90nm can move to 1V, or maybe even 0.9V I guess that will help a bit.
</strong><hr></blockquote>
I don't know about the voltage reduction, but the smaller process means a smaller die. A smaller die means more parts per wafer which means better yields and thus cheaper parts. It should also allow higher clock rates.
<strong>
Really? 2 subunits like the 7400 (VPU + VALU) or two full units or how do I have to understand this? Where can I read about it?
G4@1GHz: 10.5M RC5 keys/s
GPUL@1.8GHz: 18M RC5 keys/s
Hmm... ok.</strong><hr></blockquote>
Linear scaling by clock rate isn't surprising. In fact, its a relief. I was concerned that we'd lose some of AltiVec's magic efficiency with the introduction of IBM's VMX equivalent. RC5 isn't very bandwidth intensive, I believe, so you're not seeing the benefits of the 6.4x improvement in bandwidth.
<strong>GPUL's VMX == AltiVec, this is confirmed. It has 2 VMX units.</strong><hr></blockquote>
So aside from being "8/5-way superscalar", it has TWO AltiVec units? So theoretically double the AltiVec power of a current G4?
All in all, this is a super-nice chip.
<strong>So we're looking at by MWSF 2004 for sure, MWNY 2003 at the earliest.
Shouldn't the talk be over by now? Let's get that info rollin' in!
IBM announced the 750fx on 10/17/02 at MPF and said it would sample in 01/02. It showed up in ibooks on 5/20/02.
If the comparison is appropriate...
...and the 970 samples 4/01/03 then we should expect an announcement in July and actual products on or before 8/1/03.
10 months away.
1) Are you certain that there are two independent SIMD units? with independent registers? the ExtremeTech article says one...
2) are the SIMD units 64 bit too? and do you think they will be able to "split up" into, say, 2*32-bit operations?
Thanx,
engpjp